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 M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
RENESAS MCU
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
1.
1.1
Overview
Features
The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) is a single-chip control MCU, fabricated using highperformance silicon gate CMOS technology, embedding the M32C/80 Series CPU core. The M32C/87 Group (M32C/ 87, M32C/87A, M32C/87B) is housed in 144-pin and 100-pin plastic molded LQFP/QFP packages. With a 16-Mbyte address space, this MCU combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has a multiplier and DMAC adequate for office automation, communication devices and industrial equipment, and other high-speed processing applications.
1.1.1
Applications
Audio components, cameras, office equipment, communication devices, mobile devices, etc.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 1 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.1.2
Table 1.1 Item CPU
Specifications
Specifications (144-Pin Package) (1/2) Function Central processing unit Specification M32C/80 core (multiplier: 16 bits x 16 bits 32 bits multiply-addition operation instructions: 16 x 16 + 48 48 bits) * Basic instructions: 108 * Minimum instruction execution time: 31.3 ns (f(CPU) = 32 MHz, VCC1 = 4.2 to 5.5 V) 41.7 ns (f(CPU) = 24 MHz, VCC1 = 3.0 to 5.5 V) * Operating modes: Single-chip mode, memory expansion mode, and microprocessor mode See Tables 1.5 to 1.7 Product List. Vdet3 detection function, Vdet4 detection function, cold start/warm start determination function * Address space: 16 Mbytes * External bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 V and 5 V interfaces * Bus format: Switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) * 4 circuits: Main clock, sub clock, on-chip oscillator, PLL frequency synthesizer * Oscillation stop detection: Main clock oscillation stop detection function * Frequency divider circuit: Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 * Low power consumption features: Wait mode, stop mode * Interrupt vectors: 70 * External interrupt inputs: 14 (NMI, INT x 9, key input x 4) * Interrupt priority levels: 7 15-bit x 1 channel (with prescaler) * 4 channels, cycle steal method * Trigger sources: 43 * Transfer modes: 2 (single transfer and repeat transfer) * Can be activated by all peripheral function interrupt sources * Transfer modes: 2 (single transfer and burst transfer) * Immediate transfer, calculation transfer, and chain transfer functions 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode, Event counter 2-phase pulse signal processing (2-phase encoder input) x 3 16-bit timer x 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode 3-phase inverter control x 1 (using timer A1, timer A2, timer A4, and timer B2) On-chip dead time timer
Tables 1.1 to 1.4 list the specifications of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B).
ROM, RAM, data flash Power Supply Voltage Detection External Bus Expansion Bus/memory expansion function
Memory
Clock
Clock generation circuits
Interrupts
Watchdog Timer DMA DMAC
DMACII
Timer
Timer A
Timer B
Timer function for 3-phase motor control
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 2 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.2 Specifications (144-Pin Package) (2/2)
1. Overview
Item Function Serial Interface UART0 to UART4
UART5, UART6 A/D Converter
CRC-CCITT (X16 + X12 + X5 + 1) compliant X/Y Converter 16 bits x 16 bits Intelligent I/O 16-bit timer x 2 * Time measurement function (input capture): 8 channels * Waveform generation function (output compare): 16 channels * Communication function: Clock synchronous mode, clock asynchronous mode, HDLC data processing mode, IEBus (optional)(1)(3) * 2-phase pulse signal processing (2-phase encoder input) x 1 ROM Correction Function Address match interrupt x 8 CAN modules Supporting CAN 2.0B specification M32C/87: 16 slots x 2 channels, M32C/87A: 16 slots x 1 channel M32C/87B: none I/O Ports Programmable I/O * Input only: 1 ports * CMOS I/O: 121 with selectable pull-up resistor * N channel open drain ports: 2 Flash Memory * Erase and program voltage: 3.3 V 0.3 V or 5.0 V 0.5 V * Erase and program endurance: 100 times (all areas) * Program security: ROM code protect and ID code check * Debug functions: On-chip debug and on-board flash reprogram Operating Frequency/Supply Voltage 32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 V to VCC1 24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 V to VCC1 Current Consumption 32 mA (32 MHz, VCC1 = VCC2 = 5 V) 23 mA (24 MHz, VCC1 = VCC2 = 3.3 V) 45 A (approx. 1 MHz, VCC1 = VCC2 = 3.3 V, on-chip oscillator low-power consumption mode wait mode) 0.8 A (VCC1 = VCC2 = 3.3 V, stop mode) Operating Ambient Temperature (C) -20 to 85C, -40 to 85C (optional)(3) Package 144-pin LQFP (PLQP0144KA-A) NOTES: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. Available in UART0. 3. Please contact a Renesas sales office for optional features.
D/A Converter CRC Calculation Circuit
Specification Clock synchronous/asynchronous x 5 I2C bus, special mode 2, GCI mode, SIM mode, IrDA mode(2), IEBus (optional)(1)(3) Clock synchronous/asynchronous x 2 10-bit resolution x 34 channels (in single-chip mode) 10-bit resolution x 18 channels (in memory expansion mode and microprocessor mode) Including sample and hold function 8-bit resolution x 2 channels
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 3 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.3 Item CPU Specifications (100-Pin Package) (1/2) Function Central processing unit
1. Overview
Memory
ROM, RAM, data flash Power Supply Voltage Detection External Bus Expansion Bus/memory expansion function
Specification M32C/80 core (multiplier: 16 bits x 16 bits 32 bits multiply-addition operation instructions: 16 x 16 + 48 48 bits) * Basic instructions: 108 * Minimum instruction execution time: 31.3 ns (f(CPU) = 32 MHz, VCC1 = 4.2 to 5.5 V) 41.7 ns (f(CPU) = 24 MHz, VCC1 = 3.0 to 5.5 V) * Operating mode: Single-chip mode, memory expansion mode, and microprocessor mode See Tables 1.5 to 1.7 Product List. Vdet3 detection function, Vdet4 detection function, cold start/warm start determination function * Address space: 16 Mbytes * External bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 V and 5 V interfaces * Bus format: Switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) * 4 circuits: Main clock, sub clock, on-chip oscillator, PLL frequency synthesizer * Oscillation stop detection: Main clock oscillation stop detection function * Frequency divider circuit: Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 * Low power consumption features: Wait mode, stop mode * Interrupt vectors: 70 * External interrupt inputs: 11 (NMI, INT x 6, key input x 4) * Interrupt priority levels: 7 15-bit x 1 channel (with prescaler) * 4 channels, cycle steal method * Trigger sources: 43 * Transfer modes: 2 (single transfer and repeat transfer) * Can be activated by all peripheral function interrupt sources * Transfer modes: 2 (single transfer and burst transfer) * Immediate transfer, calculation transfer, and chain transfer functions 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode, Event counter 2-phase pulse signal processing (2-phase encoder input) x 3 16-bit timer x 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode 3-phase inverter control x 1 (using timer A1, timer A2, timer A4, and timer B2) On-chip dead time timer
Clock
Clock generation circuits
Interrupts
Watchdog Timer DMA DMAC
DMACII
Timer
Timer A
Timer B
Timer function for 3-phase motor control
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 4 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.4 Specifications (100-Pin Package) (2/2)
1. Overview
Item Function Serial Interface UART0 to UART4
UART5 A/D Converter
CRC-CCITT (X16 + X12 + X5 + 1) compliant X/Y Converter 16 bits x 16 bits Intelligent I/O 16-bit timer x 2 * Time measurement function (input capture): 8 channels * Waveform generation function (output compare): 10 channels * Communication function: Clock synchronous mode, clock asynchronous mode, HDLC data processing mode, IEBus (optional)(1)(3) * 2-phase pulse signal processing (2-phase encoder input) x 1 ROM Correction Function Address match interrupt x 8 CAN modules Supporting CAN 2.0B specification M32C/87: 16 slots x 2 channels, M32C/87A: 16 slots x 1 channel M32C/87B: none I/O Ports Programmable I/O * Input only: 1 ports * CMOS I/O: 85, selectable pull-up resistor * N channel open drain ports: 2 Flash Memory * Erase and program voltage: 3.3 V 0.3 V or 5.0 V 0.5 V * Erase and program endurance: 100 times (all areas) * Program security: ROM code protect and ID code check * Debug functions: On-chip debug and on-board flash reprogram Operating Frequency/Supply Voltage 32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 V to VCC1 24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 V to VCC1 Current Consumption 32 mA (32 MHz, VCC1 = VCC2 = 5 V) 23 mA (24 MHz, VCC1 = VCC2 = 3.3 V) 45 A (approx. 1 MHz, VCC1 = VCC2 = 3.3 V, on-chip oscillator low-power consumption mode wait mode) 0.8 A (VCC1 = VCC2 = 3.3 V, stop mode) Operating Ambient Temperature (C) -20 to 85C, -40 to 85C (optional)(3) Package 100-pin LQFP (PLQP0100KB-A) 100-pin QFP (PRQP0100JB-A) NOTES: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. Available in UART0. 3. Please contact a Renesas sales office for optional features.
D/A Converter CRC Calculation Circuit
Specification Clock synchronous/asynchronous x 5 I2C bus, special mode 2, GCI mode, SIM mode, IrDA mode(2), IEBus (optional)(1)(3) Clock synchronous/asynchronous x 1 10-bit resolution x 26 channels (in single-chip mode) 10-bit resolution x 10 channels (in memory expansion mode and microprocessor mode) Including sample and hold function 8-bit resolution x 2 channels
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 5 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.2
Table 1.5
Product List
M32C/87 Group (1) (M32C/87: 2-channel CAN module)
Package Code PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) 384 KB 24 KB 512 KB 31 KB Mask ROM 768 KB + 4 KB(1) 512 KB + 4 KB(1) 384 KB + 4 KB(1) 31 KB 24 KB 1 MB + 4 KB(1) 48 KB Flash memory ROM Capacity RAM Capacity
Tables 1.5 to 1.7 list product information. Figure 1.1 shows product numbering system. Current as of Jul. 2008
Remarks
Part Number M3087BFLGP M30879FLFP M30879FLGP M3087BFKGP M30879FKGP M30878FJGP M30876FJGP M30875FHGP M30873FHGP M30878MJ-XXXGP M30876MJ-XXXFP M30876MJ-XXXGP M30875MH-XXXGP M30873MH-XXXGP
NOTE: 1. Additional 4-Kbyte space is available for data flash memory.
Table 1.6
M32C/87 Group (2) (M32C/87A: 1-channel CAN module)
Package Code PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) 384 KB 24 KB 512 KB 31 KB 768 KB + 4 KB(1) 512 KB + 4 KB(1) 384 KB + 4 KB(1) 31 KB 24 KB 1 MB + 4 KB(1) 48 KB ROM Capacity RAM Capacity
Current as of Jul. 2008
Remarks
Part Number M3087BFLAGP M30879FLAFP M30879FLAGP M3087BFKAGP M30879FKAGP M30878FJAGP M30876FJAGP M30875FHAGP M30873FHAGP M30878MJA-XXXGP M30876MJA-XXXFP M30876MJA-XXXGP M30875MHA-XXXGP M30873MHA-XXXGP
Flash memory
Mask ROM
NOTE: 1. Additional 4-Kbyte space is available for data flash memory.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 6 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.7 M32C/87 Group (3) (M32C/87B: no CAN module)
Package Code PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) 384 KB 24 KB 512 KB 31 KB 768 KB + 4 KB(1) 512 KB + 4 KB(1) 384 KB + 4 KB(1) 31 KB 24 KB 1 MB + 4 KB(1) 48 KB ROM Capacity
1. Overview Current as of Jul. 2008
RAM Capacity Remarks
Part Number M3087BFLBGP M30879FLBFP M30879FLBGP M3087BFKBGP M30879FKBGP M30878FJBGP M30876FJBGP M30875FHBGP M30873FHBGP M30878MJB-XXXGP M30876MJB-XXXFP M30876MJB-XXXGP M30875MHB-XXXGP M30873MHB-XXXGP
Flash memory
Mask ROM
NOTE: 1. Additional 4-Kbyte space is available for data flash memory.
Part No.
M30 87 6 M J
-XXX GP
Package type option FP: PRQP0100JB-A (100P6S-A) GP: PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) ROM Number: Omitted for the Flash Memory Version Classification Blank: M32C/87 A: M32C/87A B: M32C/87B ROM capacity H: 384 Kbytes J: 512 Kbytes K: 768 Kbytes L: 1024 Kbytes Memory type M: Mask ROM version F: Flash memory version RAM capacity, pin count, etc (The value itself has no specific meaning.) M32C/87 Group M16C Family
Figure 1.1
Product Numbering System
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 7 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.3
Block Diagram
Figure 1.2 shows a block diagram of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B).
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7


Internal peripheral functions
Timers (16 bits) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit Watchdog timer (15 bits) Serial interface: 7 channels(3) 10-bit A/D converter: 1 circuit 34 channels for input(2) 8-bit D/A converters: 2 circuits X/Y converter: 16 bits X 16 bits DMAC: 4 channels Clock generation circuits: XIN-XOUT XCIN-XCOUT On-chip oscillator PLL frequency synthesizer CRC calculation circuit (CCITT): X16 + X12 + X5 + 1 DMACII
Intelligent I/O Time measurement function: 8 channels Waveform generation function: 16 channels(4) Communication function: clock synchronous serial interface, UART, HDLC data processing, IEBus
M32C/80 Series CPU core
R1H R1L R0H R0L R1H R1L R1H R1L R2 R3 A0 A1 FB FLG INTB ISP USP PC SVF SVP VCT
Memory
ROM
RAM
CAN modules:2 channels(5)
Port P13(1) Port P12(1) Port P11(1) Port P15(1)
SB
Multiplier

Port P14(1) Port P10 Port P9 P8_5 Port P8
8
8
5
8
7
8
8
7
NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. 34 channels are available in the 144-pin package. 26 channels are available in the 100-pin package. 3. 6 channels are available in the 100-pin package. 4. 10 channels are available in the 100-pin package. 5. M32C/87A has 1 channel. M32C/87B has no CAN module.
Figure 1.2
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Block Diagram
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 8 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.4
Pin Assignments
Figures 1.3 to 1.5 show pin assignments (top view).
( note 7) ( note 7)
P1_1 / D9 P1_2 / D10 P1_3 / D11 P1_4 / D12 P1_5 / INT3 / D13 P1_6 / INT4 / D14 P1_7 / INT5 / D15 P2_0 / AN2_0 / A0, [A0/D0] P2_1 / AN2_1 / A1, [A1/D1] P2_2 / AN2_2 / A2, [A2/D2] P2_3 / AN2_3 / A3, [A3/D3] P2_4 / AN2_4 / A4, [A4/D4] P2_5 / AN2_5 / A5, [A5/D5] P2_6 / AN2_6 / A6, [A6/D6] P2_7 / AN2_7 / A7, [A7/D7] VSS P3_0/ A8, [A8/D8](7) VCC2 P12_0 / TXD6 P12_1 / CLK6 P12_2 / RXD6 P12_3 / CTS6 / RTS6 P12_4 P3_1 / A9, [A9/D9] P3_2 / A10, [A10/D10] P3_3 / A11, [A11/D11] P3_4 / A12, [A12/D12] P3_5/ A13, [A13/D13] P3_6/ A14, [A14/D14] P3_7 / A15, [A15/D15] P4_0 / A16 P4_1 / A17 VSS P4_2 / A18 VCC2 P4_3 / A19
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
D8 / P1_0 D7 / AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 P11_4 OUTC1_3 / INPC1_3 / P11_3 ISRXD1 / OUTC1_2 / INPC1_2 / P11_2 ISCLK1 / OUTC1_1 / INPC1_1 / P11_1 ISTXD1 / OUTC1_0 / INPC1_0 / P11_0 D3 / AN0_3 / P0_3 D2 / AN0_2 / P0_2 D1 / AN0_1 / P0_1 D0 / AN0_0 / P0_0 AN15_7 / RTS6 / CTS6 / P15_7 AN15_6 / CLK6 / P15_6 AN15_5 / RXD6 / P15_5 AN15_4 / TXD6 / P15_4 AN15_3 / RTS5 / CTS5 / P15_3 AN15_2 / ISRXD0 / RXD5 / P15_2 AN15_1 / ISCLK0 / CLK5 / P15_1 VSS AN15_0 / ISTXD0 / TXD5 / P15_0 VCC1 AN_7 / RTP3_3 / KI3 / P10_7 AN_6 / RTP3_2 / KI2 / P10_6 AN_5 / RTP3_1 / KI1 / P10_5 AN_4 / RTP3_0 / KI0 / P10_4 AN_3 / RTP1_3 / P10_3 AN_2 / RTP1_2 / P10_2 AN_1 / RTP1_1 / P10_1 AVSS AN_0 / RTP1_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

M32C/87 Group
(M32C/87, M32C/87A, M32C/87B) PLQP0144KA-A (144P6Q-A) (top view)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P12_5 P12_6 P12_7 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P13_0 / OUTC2_4 P13_1 / OUTC2_5 VCC2 P13_2 / OUTC2_6 VSS P13_3 / OUTC2_3 P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P13_4 / OUTC2_0 / ISTXD2 / IEOUT P13_5 / OUTC2_2 / ISRXD2 / IEIN P13_6 / OUTC2_1 / ISCLK2 P13_7 / OUTC2_7 P6_0 / RTP0_0 / CTS0 / RTS0 / SS0 P6_1 / RTP0_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 / IrDAIN P6_3 / TXD0 / SDA0 / SRXD0 / IrDAOUT P6_4(3) P6_5 / CLK1 VSS P6_6 / RXD1 / SCL1 / STXD1 VCC1 P6_7 / TXD1 / SDA1 / SRXD1 P7_0(2) (4)
(note 6)
1
2
3
4
5
6
7
8
NOTES: 1. P7_1 / TA0IN / TB5IN / RTP0_3 / RXD2 / SCL2 / STXD2 / INPC1_7 / OUTC1_7 / OUTC2_2 / ISRXD2 / IEIN 2. P7_0 / TA0OUT / RTP0_2 / TXD2 / SDA2 / SRXD2 / INPC1_6 / OUTC1_6 / OUTC2_0 / ISTXD2 / IEOUT 3. P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 4. P7_0 and P7_1 are N-channel open drain output ports. 5. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A. 6. Refer to Package Dimensions for the pin1 position on the package. 7. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.3
Pin Assignment for 144-Pin Package
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 9 of 85
/ P9_6 / P9_5 / P9_4 / P9_3 / P9_2 / P9_1 / P9_0 P14_6 P14_5 P14_4 P14_3 P14_2 P14_1 P14_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC1 NMI / P8_5 INT2 / P8_4 (5) CAN1IN / CAN0IN / INT1 / P8_3 (5) CAN1OUT / CAN0OUT / INT0 / P8_2 OUTC1_5 / INPC1_5 / RTS5 / CTS5 / RTP2_3 / U / TA4IN / P8_1 ISRXD0 / RXD5 / U / TA4OUT / P8_0 ISCLK0 / OUTC1_4 / INPC1_4 / CAN0IN / CLK5 / RTP2_2 / TA3IN / P7_7 ISTXD0 / OUTC1_3 / INPC1_3 / TXD5 / CAN0OUT / TA3OUT / P7_6 ISRXD0 / OUTC1_2 / INPC1_2 / RTP2_1 / W / TA2IN / P7_5 ISCLK1 / OUTC1_1 / INPC1_1 / RTP2_0 / W / TA2OUT / P7_4 ISTXD1 / OUTC1_0 / INPC1_0 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3 CLK2 / V / TA1OUT / P7_2 (1) (4) P7_1 ANEX1 / SRXD4 / SDA4 / TXD4 / CAN1OUT (5) ANEX0 / CAN1WU / CAN1IN / CLK4 DA1 / SS4 / RTS4 / CTS4 / TB4IN DA0 / SS3 / RTS3 / CTS3 / TB3IN ISTXD2 / IEOUT / OUTC2_0 / SRXD3 / SDA3 / TXD3 / TB2IN ISRXD2 / IEIN / STXD3 / SCL3 / RXD3 / TB1IN CLK3 / TB0IN INT8 / INT7 / INT6 / OUTC1_7 / INPC1_7 / OUTC1_6 / INPC1_6 / OUTC1_5 / INPC1_5 / OUTC1_4 / INPC1_4 /
(5)
9
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.8
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BYTE 16 CNVSS 17 XCIN 18 XCOUT 19 RESET 20 XOUT 21 VSS 22 XIN 23 VCC1 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 VCC1 40 P6_6 RXD1/SCL1/STXD1 NOTE: 1. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A. P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 NMI INT2 INT1 INT0 TA4OUT/U TA3IN/RTP2_2 TA3OUT TA2IN/W/RTP2_1 TA2OUT/W/ RTP2_0 TA1IN/V TA1OUT/V TA0IN/TB5IN/ RTP0_3 CTS2/RTS2/SS2 CLK2 RXD2/SCL2/STXD2 INPC1_7/OUTC1_7/ OUTC2_2/ISRXD2/IEIN INPC1_6/OUTC1_6/ OUTC2_0/ISTXD2/IEOUT CAN0IN/CAN1IN CAN0OUT/CAN1OUT TA4IN/U/RTP2_3 CTS5/RTS5 RXD5 CLK5/CAN0IN TXD5/CAN0OUT INPC1_5/OUTC1_5 ISRXD0 INPC1_4/OUTC1_4/ ISCLK0 INPC1_3/OUTC1_3/ ISTXD0 INPC1_2/OUTC1_2/ ISRXD1 INPC1_1/OUTC1_1/ ISCLK1 INPC1_0/OUTC1_0/ ISTXD1 P8_7 P8_6 Control Pin
1. Overview
144-Pin Package List of Pin Names (1/4)
Port P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 P14_6 P14_5 P14_4 P14_3 P14_2 P14_1 P14_0 INT8 INT7 INT6 INPC1_7/OUTC1_7 INPC1_6/OUTC1_6 INPC1_5/OUTC1_5 INPC1_4/OUTC1_4 TB4IN TB3IN TB2IN TB1IN TB0IN Interrupt Pin Timer Pin UART/CAN Pin(1) TXD4/SDA4/SRXD4/ CAN1OUT CLK4/CAN1IN/CAN1WU CTS4/RTS4/SS4 CTS3/RTS3/SS3 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3 OUTC2_0/IEOUT/ISTXD2 IEIN/ISRXD2 Intelligent I/O Pin Analog Pin ANEX1 ANEX0 DA1 DA0 Bus Control Pin
TA0OUT/RTP0_2 TXD2/SDA2/SRXD2 TXD1/SDA1/SRXD1
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 10 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.9
Pin No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 VSS 58 59 VCC2 60 61 63 64 65 66 67 68 69 70 71 72 73 74 VCC2 75 76 VSS 77 78 79 80 P4_1 P4_0 P3_7 P3_6 A17 A16 P4_2 A18 P13_1 P13_0 P5_2 P5_1 P5_0 P12_7 P12_6 P12_5 P4_7 P4_6 P4_5 P4_4 P4_3 OUTC2_5 OUTC2_4 P13_2 OUTC2_6 Control Pin
1. Overview
144-Pin Package List of Pin Names (2/4)
Port Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin Bus Control Pin
41 VSS P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P13_7 P13_6 P13_5 P13_4 P5_7 P5_6 P5_5 P5_4 P13_3 OUTC2_3 RTP0_1 RTP0_0 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0/ IrDAOUT RXD0/SCL0/STXD0/ IrDAIN CLK0 CTS0/RTS0/SS0 OUTC2_7 OUTC2_1/ISCLK2 OUTC2_2/ISRXD2/ IEIN OUTC2_0/ISTXD2/ IEOUT RDY ALE HOLD HLDA/ALE OUTC2_1/ISCLK2
62 CLKOUT P5_3
BCLK/ALE RD WRH/BHE WRL/WR
CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19
A15,[A15/D15] A14,[A14/D14]
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 11 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.10
Pin No. 81 82 83 84 85 86 87 88 89 90 91 VCC2 92 93 VSS 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P11_4 P11_3 P11_2 P11_1 P11_0 P0_3 P0_2 INPC1_3/OUTC1_3 INPC1_2/OUTC1_2/ ISRXD1 INPC1_1/OUTC1_1/ ISCLK1 INPC1_0/OUTC1_0/ ISTXD1 AN0_3 AN0_2 D3 D2 AN0_7 AN0_6 AN0_5 AN0_4 INT5 INT4 INT3 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 P3_0 Control Pin
1. Overview
144-Pin Package List of Pin Names (3/4)
Port P3_5 P3_4 P3_3 P3_2 P3_1 P12_4 P12_3 P12_2 P12_1 P12_0 CTS6/RTS6 RXD6 CLK6 TXD6 A8,[A8/D8] A7,[A7/D7] A6,[A6/D6] A5,[A5/D5] A4,[A4/D4] A3,[A3/D3] A2,[A2/D2] A1,[A1/D1] A0,[A0/D0] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin Bus Control Pin A13,[A13/D13] A12,[A12/D12] A11,[A11/D11] A10,[A10/D10] A9,[A9/D9]
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 12 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.11
Pin No. 121 122 123 124 125 126 127 128 129 130 VSS 131 132 VCC1 133 134 135 136 137 138 139 140 AVSS 141 142 VREF 143 AVCC 144 P9_7 RXD4/SCL4/STXD4 ADTRG P10_0 RTP1_0 AN_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 KI3 KI2 KI1 KI0 RTP3_3 RTP3_2 RTP3_1 RTP3_0 RTP1_3 RTP1_2 RTP1_1 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 P15_0 TXD5 ISTXD0 AN15_0 Control Pin
1. Overview
144-Pin Package List of Pin Names (4/4)
Port P0_1 P0_0 P15_7 P15_6 P15_5 P15_4 P15_3 P15_2 P15_1 CTS6/RTS6 CLK6 RXD6 TXD6 CTS5/RTS5 RXD5 CLK5 ISRXD0 ISCLK0 Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin AN0_1 AN0_0 AN15_7 AN15_6 AN15_5 AN15_4 AN15_3 AN15_2 AN15_1 Bus Control Pin D1 D0
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 13 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
( note 6) ( note 6)
P1_0 / D8 P1_1 / D9 P1_2 / D10 P1_3 / D11 P1_4 / D12 P1_5 / INT3 / D13 P1_6 / INT4 / D14 P1_7 / INT5 / D15 P2_0 / AN2_0 / A0, [A0/D0] P2_1 / AN2_1 / A1, [A1/D1] P2_2 / AN2_2 / A2, [A2/D2] P2_3 / AN2_3 / A3, [A3/D3] P2_4 / AN2_4 / A4, [A4/D4] P2_5 / AN2_5 / A5, [A5/D5] P2_6 / AN2_6 / A6, [A6/D6] P2_7 / AN2_7 / A7, [A7/D7] VSS P3_0 / A8, [A8/D8](6) VCC2 P3_1 / A9, [A9/D9] P3_2 / A10, [A10/D10] P3_3 / A11, [A11/D11] P3_4 / A12, [A12/D12] P3_5 / A13, [A13/D13] P3_6 / A14, [A14/D14] P3_7 / A15, [A15/D15] P4_0 / A16 P4_1 / A17 P4_2 / A18 P4_3 / A19
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
D7 / AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 D3 / AN0_3 / P0_3 D2 / AN0_2 / P0_2 D1 / AN0_1 / P0_1 D0 / AN0_0 / P0_0 AN_7 / RTP3_3 / KI3 / P10_7 AN_6 / RTP3_2 / KI2 / P10_6 AN_5 / RTP3_1 / KI1 / P10_5 AN_4 / RTP3_0 / KI0 / P10_4 AN_3 / RTP1_3 / P10_3 AN_2 / RTP1_2 / P10_2 AN_1 / RTP1_1 / P10_1 AVSS AN_0 / RTP1_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
51

M32C/87 Group
(M32C/87,M32C/87A,M32C/87B) PRQP0100JB-A (100P6S-A) (top view)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P6_0 / RTP0_1 / CTS0 / RTS0 / SS0 P6_1 / RTP0_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 / IrDAIN P6_3 / TXD0 / SDA0 / SRXD0 / IrDAOUT P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 P6_5 / CLK1 P6_6 / RXD1 / SCL1 / STXD1 P6_7 /TXD1 / SDA1 / SRXD1
( note 5)
1
2
3
4
5
6
7
8
NOTES: 1. P7_1 / TA0IN / TB5IN / RTP0_3 / RXD2 / SCL2 / STXD2 / INPC1_7 / OUTC1_7 / OUTC2_2 / ISRXD2 / IEIN 2. P7_0 / TA0OUT / RTP0_2 / TXD2 / SDA2 / SRXD2 / INPC1_6 / OUTC1_6 / OUTC2_0 / ISTXD2 / IEOUT 3. P7_0 and P7_1 are N-channel open drain output ports. 4. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A. 5. Refer to Package Dimensions for the pin1 position on the package. 6. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.4
Pin Assignment for 100-Pin Package
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 14 of 85
ANEX1 / CAN1OUT / SRXD4 / SDA4 / TXD4 / P9_6 (4) ANEX0 / CAN1WU / CAN1IN / CLK4 / P9_5 DA1 / SS4 / RTS4 / CTS4 / TB4IN / P9_4 DA0 / SS3 / RTS3 / CTS3 / TB3IN / P9_3 ISTXD2 / IEOUT / OUTC2_0 / SRXD3 / SDA3 / TXD3 / TB2IN / P9_2 ISRXD2 / IEIN / STXD3 / SCL3 / RXD3 / TB1IN / P9_1 CLK3 / TB0IN / P9_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC1 NMI / P8_5 INT2 / P8_4 (4) CAN1IN / CAN0IN / INT1 / P8_3 (4) CAN1OUT / CAN0OUT / INT0 / P8_2 OUTC1_5 / INPC1_5 / RTS5 / CTS5 / RTP2_3 / U / TA4IN / P8_1 ISRXD0 / RXD5 / U / TA4OUT / P8_0 (4) ISCLK0 / OUTC1_4 / INPC1_4 / CAN0IN / CLK5 / RTP2_2 / TA3IN / P7_7 (4) ISTXD0 / OUTC1_3 / INPC1_3 / CAN0OUT / TXD5 / TA3OUT / P7_6 ISRXD1 / OUTC1_2 / INPC1_2 / RTP2_1 / W / TA2IN / P7_5 ISCLK1 / OUTC1_1 / INPC1_1 / RTP2_0 / W / TA2OUT / P7_4 ISTXD1 / OUTC1_0 / INPC1_0 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3 CLK2 / V / TA1OUT / P7_2 (1)(3) P7_1 (2)(3) P7_0
(4)
9
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
( note 6) ( note 6) P1_3 / D11 P1_4 / D12 P1_5 / INT3 / D13 P1_6 / INT4 / D14 P1_7 / INT5 / D15 P2_0 / AN2_0 / A0, [A0/D0] P2_1 / AN2_1 / A1, [A1/D1] P2_2 / AN2_2 / A2, [A2/D2] P2_3 / AN2_3 / A3, [A3/D3] P2_4 / AN2_4 / A4, [A4/D4] P2_5 / AN2_5 / A5, [A5/D5] P2_6 / AN2_6 / A6, [A6/D6] P2_7 / AN2_7 / A7, [A7/D7] VSS P3_0 / A8, [A8/D8](6) VCC2 P3_1 / A9, [A9/D9] P3_2 / A10, [A10/D10] P3_3 / A11, [A11/D11] P3_4 / A12, [A12/D12] P3_5 / A13, [A13/D13] P3_6 / A14, [A14/D14] P3_7 / A15, [A15/D15] P4_0 / A16 P4_1 / A17
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D10 / P1_2 D9 / P1_1 D8 / P1_0 D7 / AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 D3 / AN0_3 / P0_3 D2 / AN0_2 / P0_2 D1 / AN0_1 / P0_1 D0 / AN0_0 / P0_0 AN_7 / RTP3_3 / KI3 / P10_7 AN_6 / RTP3_2 / KI2 / P10_6 AN_5 / RTP3_1 / KI1 / P10_5 AN_4 / RTP3_0 / KI0 / P10_4 AN_3 / RTP1_3 P10_3 AN_2 / RTP1_2 / P10_2 AN_1 / RTP1_1 / P10_1 AVSS AN_0 / RTP1_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7 (4) ANEX1 / CAN1OUT / SRXD4 / SDA4 / TXD4 / P9_6 (4) ANEX0 / CAN1WU / CAN1IN / CLK4 / P9_5
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

M32C/87 Group
(M32C/87,M32C/87A,M32C/87B) PLQP0100KB-A (100P6Q-A) (top view)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
P4_2 / A18 P4_3 / A19 P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P6_0 / RTP0_0 / CTS0 / RTS0 / SS0 P6_1 / RTP0_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 / IrDAIN P6_3 / TXD0 / SDA0 / SRXD0 / IrDAOUT P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 P6_5 / CLK1 P6_6 / RXD1 / SCL1 / STXD1 P6_7 /TXD1 / SDA1 / SRXD1 P7_0(2)(3) P7_1(1)(3) P7_2 / TA1OUT / V / CLK2
( note 5)
NOTES: 1. P7_1 / TA0IN / TB5IN / RTP0_3 / RXD2 / SCL2 / STXD2 / INPC1_7 / OUTC1_7 / OUTC2_2 / ISRXD2 / IEIN 2. P7_0 / TA0OUT / RTP0_2 / TXD2 / SDA2 / SRXD2 / INPC1_6 / OUTC1_6 / OUTC2_0 / ISTXD2 / IEOUT 3. P7_0 and P7_1 are N-channel open drain output ports. 4. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A. 5. Refer to Package Dimensions for the pin1 position on the package. 6. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.5
Pin Assignment for 100-Pin Package
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 15 of 85
DA1 / SS4 / RTS4 / CTS4 / TB4IN / P9_4 DA0 / SS3 / RTS3 / CTS3 / TB3IN / P9_3 ISTXD2 / IEOUT / OUTC2_0 / SRXD3 / SDA3 / TXD3 / TB2IN / P9_2 ISRXD2 / IEIN / STXD3 / SCL3 / RXD3 / TB1IN / P9_1 CLK3 / TB0IN / P9_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC1 NMI / P8_5 INT2 / P8_4 (4) CAN1IN / CAN0IN / INT1 / P8_3 (4) CAN1OUT / CAN0OUT / INT0 / P8_2 OUTC1_5 / INPC1_5 / RTS5 / CTS5 / RTP2_3 / U / TA4IN / P8_1 ISRXD0 / RXD5 / U / TA4OUT / P8_0 (4)ISCLK0 / OUTC1_4 / INPC1_4 / CAN0IN / CLK5 / RTP2_2 / TA3IN / P7_7 (4) ISTXD0 / OUTC13 / INPC13 / CAN0OUT / TXD5 / TA3OUT / P7_6 ISRXD1 / OUTC1_2 / INPC1_2 / RTP2_1 / W / TA2IN / P7_5 ISCLK1 / OUTC1_1 / INPC1_1 / RTP2_0 / W / TA2OUT / P7_4 ISTXD1 / OUTC1_0 / INPC1_0 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.12
Pin No. FP GP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 99 100 1 2 3 4 5 6 7 8 9 BYTE CNVSS XCIN XCOUT P8_7 P8_6
1. Overview
100-Pin Package List of Pin Names (1/3)
Port P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 TB4IN TB3IN TB2IN TB1IN TB0IN
Interrupt Pin
Control Pin
Timer Pin
UART/CAN Pin(1) TXD4/SDA4/SRXD4/ CAN1OUT CLK4/CAN1IN/ CAN1WU CTS4/RTS4/SS4 CTS3/RTS3/SS3 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3
Intelligent I/O Pin
Analog Bus Control Pin Pin ANEX1 ANEX0 DA1 DA0
OUTC2_0/IEOUT/ISTXD2
IEIN/ISRXD2
10 RESET 11 XOUT 12 VSS 13 XIN 14 VCC1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 RTP0_1 RTP0_0 NMI INT2 INT1 INT0 TA4OUT/U TA3IN/RTP2_2 TA3OUT TA2IN/W/RTP2_1 TA2OUT/W/ RTP2_0 TA1IN/V TA1OUT/V TA0IN/TB5IN/ RTP0_3 CTS2/RTS2/SS2 CLK2 RXD2/SCL2/STXD2 INPC1_7/OUTC1_7/ OUTC2_2/ISRXD2/IEIN
INPC1_6/OUTC1_6/ OUTC2_0/ISTXD2/IEOUT
CAN0IN/CAN1IN CAN0OUT/CAN1OUT TA4IN/U/RTP2_3 CTS5/RTS5 RXD5 CLK5/CAN0IN TXD5/CAN0OUT INPC1_5/OUTC1_5 ISRXD0 INPC1_4/OUTC1_4/ ISCLK0 INPC1_3/OUTC1_3/ ISTXD0 INPC1_2/OUTC1_2 ISRXD1 INPC1_1/OUTC1_1/ ISCLK1 INPC1_0/OUTC1_0/ ISTXD1
TA0OUT/RTP0_2 TXD2/SDA2/SRXD2 TXD1/SDA1/SRXD1 RXD1/SCL1/STXD1 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0/ IrDAOUT RXD0/SCL0/STXD0/ IrDAIN CLK0 CTS0/RTS0/SS0
OUTC2_1/ISCLK2
RDY ALE
NOTE: 1. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 16 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.13
Pin No. FP GP 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 39 40 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VCC2 61 62 VSS 63 64 65 66 67 68 69 70
1. Overview
100-Pin Package List of Pin Names (2/3)
Port P5_5 P5_4 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0
Interrupt Pin
Control Pin
Timer Pin
UART/CAN Pin
Intelligent I/O Pin
Analog Pin
Bus Control Pin HOLD HLDA/ALE BCLK/ALE RD WRH/BHE WRL/WR CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19 A18 A17 A16 A15,[A15/D15] A14,[A14/D14] A13,[A13/D13] A12,[A12/D12] A11,[A11/D11] A10,[A10/D10] A9,[A9/D9] A8,[A8/D8] A7,[A7/D7] A6,[A6/D6] A5,[A5/D5] A4,[A4/D4] A3,[A3/D3] A2,[A2/D2] A1,[A1/D1] A0,[A0/D0]
41 CLKOUT P5_3
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 17 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.14
Pin No. FP GP 73 71 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 AVSS 95 96 VREF 97 AVCC 98 P10_0 RTP1_0 AN_0
1. Overview
100-Pin Package List of Pin Names (3/3)
Port P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1
Interrupt Pin
Control Pin
Timer Pin
UART/CAN Pin
Intelligent I/O Pin
Analog Bus Control Pin Pin D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
INT5 INT4 INT3
KI3 KI2 KI1 KI0
RTP3_3 RTP3_2 RTP3_1 RTP3_0 RTP1_3 RTP1_2 RTP1_1
AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1
P9_7
RXD4/SCL4/STXD4
ADTRG
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 18 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.5
Pin Functions
Pin Functions (100-Pin and 144-Pin Packages) (1/4)
Symbol VCC1,VCC2 VSS AVCC AVSS RESET CNVSS I/O Supply Description Type Voltage - - Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin. The input condition of VCC1 VCC2 must be met. - VCC1 Power supply input pins to the A/D converter and D/A converter. Connect the AVCC pin to VCC1, and the AVSS pin to VSS. I I VCC1 VCC1 The MCU is placed in the reset state while applying an "L" signal to the RESET pin. This pin switches processor mode. Apply an "L" to the CNVSS pin to start up in single-chip mode, or an "H" to start up in microprocessor mode (mask ROM, flash memory version) and boot mode (flash memory version). This pin switches a data bus width in external memory space 3. A data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H". Fix to either "L" or "H". Apply an "L" to the BYTE pin in single-chip mode. Data (D0 to D7) input/output pins while accessing an external memory space with separate bus. Data (D8 to D15) input/output pins while accessing an external memory space with 16-bit separate bus. Address bits (A0 to A22) output pins. Inverted address bit (A23) output pin. Data (D0 to D7) input/output and 8 low-order address bits (A0 to A7) output are performed by time-sharing these pins while accessing an external memory space with multiplexed bus. Data (D8 to D15) input/output and 8 middle-order address bits (A8 to A15) output are performed by time-sharing these pins while accessing an external memory space with 16-bit multiplexed bus. Chip-select signal output pins used to specify external devices. WRL, WRH, (WR, BHE) and RD signal output pins. WRL and WRH can be switched with WR and BHE by a program. * WRL, WRH and RD are selected: If external data bus is 16 bits wide, data is written to an even address in external memory space while an "L" is output from the WRL pin. Data is written to an odd address while an "L" is output from the WRH pin. Data is read while an "L" is output from the RD pin. * WR, BHE and RD are selected: Data is written while an "L" is output from the WR pin. Data is read while an "L" is output from the RD pin. Data in odd address is accessed while an "L" is output from the BHE pin. Select WR, BHE and RD when an external data bus is 8 bits wide. ALE signal is used for the external devices to latch address signals when the multiplexed bus is selected. The MCU is placed in a hold state while an "L" signal is applied to the HOLD pin. The HLDA pin outputs an "L" while the MCU is placed in a hold state. Bus is placed in a wait state while an "L" signal is applied to the RDY pin.
Table 1.15
Type Power supply Analog power supply input Reset input CNVSS
External data bus width select input Bus control Pins
BYTE
I
VCC1
D0 to D7 D8 to D15 A0 to A22 A23 A0/D0 to A7/D7 A8/D8 to A15/D15 CS0 to CS3 WRL/WR WRH/BHE RD
I/O I/O O O I/O
VCC2 VCC2 VCC2 VCC2 VCC2
I/O
VCC2
O O
VCC2 VCC2
ALE HOLD HLDA RDY
O I O I
VCC2 VCC2 VCC2 VCC2
I: Input
O: Output
I/O: Input and output
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.16
Type Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input NMI interrupt input Timer A XIN XOUT XCIN XCOUT BCLK CLKOUT INT0 to INT2 INT3 to INT5 NMI TA0OUT to TA4OUT TA0IN to TA4IN TB0IN to TB5IN U, U, V, V, W, W CTS0 to CTS5 RTS0 to RTS5 CLK0 to CLK5 RXD0 to RXD5 TXD0 to TXD5 SDA0 to SDA4 SCL0 to SCL4 STXD0 to Serial STXD4 interface special function SRXD0 to SRXD4 SS0 to SS4 IrDA CAN(1) IrDAIN IrDAOUT CAN0IN, CAN1IN CAN0OUT, CAN1OUT CAN1WU
1. Overview
Pin Functions (100-Pin and 144-Pin Packages) (2/4)
Symbol I/O Supply Description Type Voltage I VCC1 Input/output pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To O VCC1 apply an external clock, apply it to XIN and leave XOUT open. I O O O I I I I/O I I O VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 NMI interrupt input pin. Connect the NMI pin to VCC1 via a resistor when the NMI interrupt is not used. Timer A0 to A4 input/output pins. (TA0OUT is N-channel open drain output.) Timer A0 to A4 input pins. Timer B0 to B5 input pins. Three-phase motor control timer output pins. Input/output pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To apply an external clock, apply it to XCIN and leave XCOUT open. Bus clock output pin. The CLKOUT pin outputs the clock having the same frequency as fC, f8, or f32. INT interrupt input pins.
Timer B Three-phase motor control timer output Serial interface
I O I/O I O I/O I/O O I I I O I O I
VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1
Input pins to control data transmission. Output pins to control data reception. Serial clock input/output pins. Serial data input pins. Serial data output pins. (TXD2 is N-channel open drain output.) Serial data input/output pins. (SDA2 is N-channel open drain output.) Serial clock input/output pins. (SCL2 is N-channel open drain output.) Serial data output pins when slave mode is selected. (STXD2 is N-channel open drain output.) Serial data input pins when slave mode is selected. Control input pins used in the serial interface special mode. IrDA serial data input pin. IrDA serial data output pin. Received data input pins for the CAN communication function. Transmit data output pins for the CAN communication function. CAN wake-up interrupt input pin.
I2C mode
I: Input O: Output I/O: Input and output NOTE: 1. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.17
Type Intelligent I/O
1. Overview
Pin Functions (100-Pin and 144-Pin Package) (3/4)
Symbol INPC1_0 to INPC1_3 INPC1_4 to INPC1_7 OUTC1_0 to OUTC1_3 OUTC1_4 to OUTC1_7 OUTC2_0 to OUTC2_2 ISCLK0 ISCLK1, ISCLK2 ISRXD0 ISRXD1, ISRXD2 ISTXD0 ISTXD1, ISTXD2 IEIN IEOUT I/O Supply Description Type Voltage I VCC1/ Input pins for the time measurement function. VCC2(1) I VCC1 O VCC1/ Output pins for the waveform generation function. VCC2(1) (OUTC1_6/OUTC2_0 and OUTC1_7/OUTC2_2 assigned to ports 7_0 and 7_1 are N-channel open drain output.) VCC1 VCC1/ VCC2(1) VCC1 VCC1/ VCC2(1) VCC1 VCC1/ VCC2(1) VCC1 VCC1/ VCC2(1) VCC1/ VCC2(1) VCC1/ VCC2(1) - VCC1 VCC2
O O I/O I/O I I O O I O I I I
Clock input/output pins for the intelligent I/O communication function. Data input pins for the intelligent I/O communication function.
Data output pins for the intelligent I/O communication function. (ISTXD2 assigned to port 7_0 is N-channel open drain output.) Data input pin for the intelligent I/O communication function. Data output pin for the intelligent I/O communication function. (IEOUT assigned to port 7_0 is N-channel open drain output.) The VREF pin supplies the reference voltage to the A/D converter and D/A converter. Analog input pins for the A/D converter.
Reference voltage input A/D converter
VREF AN_0 to AN_7 AN0_0 to AN0_7, AN2_0 to AN2_7 ADTRG ANEX0
I I/O I O O
VCC1 VCC1 VCC1 VCC1 VCC1
External trigger input pin for the A/D converter. Extended analog input pin for the A/D converter or output pin in external op-amp connection mode. Extended analog input pin for the A/D converter. Output pins for the D/A converter. These pins function as real-time ports. (RTP0_2 and RTP0_3 are N-channel open drain output.)
ANEX1 D/A converter DA0, DA1 Real-time port RTP0_0 to RTP0_3 RTP1_0 to RTP1_3 RTP2_0 to RTP2_3 RTP3_0 to RTP3_3
I: Input O: Output I/O: Input and output NOTE: 1. Only VCC1 can be used in the 100-pin package.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.18
Type I/O port
1. Overview
Pin Functions (100-Pin and 144-Pin Package) (4/4)
I/O Supply Description Type Voltage P0_0 to P0_7, I/O VCC2 8-bit CMOS I/O ports. The Port Pi Direction Register (i = 0 to 15) P1_0 to P1_7, determines if each pin is used as an input port or an output port. P2_0 to P2_7, The Pull-Up Control Registers determine if the input ports, divided P3_0 to P3_7, into groups of four, are pulled up or not. P4_0 to P4_7, P5_0 to P5_7 P6_0 to P6_7, I/O VCC1 These 8-bit I/O ports are functionally equivalent to P0. P7_0 to P7_7, (P7_0 and P7_1 are N-channel open drain output.) P9_0 to P9_7, P10_0 to P10_7 P8_0 to P8_4 I/O VCC1 These I/O ports are functionally equivalent to P0. P8_6, P8_7 P8_5 I VCC1 Shares the pin with NMI. Input port to read NMI pin level. Symbol KI0 to KI3 I VCC1 Key input interrupt input pins.
Input port Key input interrupt input I: Input
O: Output
I/O: Input and output
Table 1.19
Type INT Interrupt Input Serial interface
Pin Functions (144-Pin Package Only)
Symbol INT6 to INT8 CTS6 RTS6 CLK6 RXD6 TXD6 I/O Supply Type Voltage I VCC1 INT interrupt input pins. I O I/O I O O I I/O VCC1/ VCC2 VCC1/ VCC2 VCC1/ VCC2 VCC1/ VCC2 VCC1/ VCC2 VCC2 VCC1 VCC2 Description
Input pin to control data transmission. Output pin to control data reception. Serial clock input/output pin. Serial data input pin. Serial data output pin. Output pins for the waveform generation function. Analog input pins for the A/D converter. These I/O ports are functionally equivalent to P0.
Intelligent I/O A/D converter I/O port
OUTC2_3 to OUTC2_7 AN15_0 to AN15_7 P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7 P14_0 to P14_6, P15_0 to P15_7
I/O
VCC1
These I/O ports are functionally equivalent to P0.
I: Input
O: Output
I/O: Input and output
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There are two sets of register banks.
b31
b15
b0
General registers
R2 R2 R3 R3
b23
R0H R0H R1H R1H A0 A0 A1 A1 SB SB FB FB USP ISP INTB PC
b15
R2 R2 R3 R3
R0L R0L R1L R1L
Data registers(1)
Address registers(1) Static base register(1) Frame base register(1) User stack pointer Interrupt stack pointer Interrupt table register Program counter
FLG
b8 b7 b0
Flag register
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved Processor interrupt priority level Reserved
High-speed interrupt registers
b15 b23
b0
SVF SVP VCT
b7 b0
Flag save register PC save register Vector register
DMAC-associated registers
b15
DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DRA0 DRA1 DSA0 DSA1
DMA mode registers DMA transfer count registers DMA transfer count reload registers DMA memory address registers DMA memory address reload registers DMA SFR address registers
b23
NOTE: 1. These registers comprise a register bank. There are two sets of register banks (register bank 0 and register bank 1).
Figure 2.1
CPU Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
2. Central Processing Unit (CPU)
2.1 2.1.1
General Registers Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1.
2.1.2
Address Registers (A0 and A1)
A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3 2.1.4 2.1.5
Static Base Register (SB) Frame Base Register (FB) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
SB is a 24-bit register used for SB-relative addressing.
FB is a 24-bit register used for FB-relative addressing.
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.
2.1.6 2.1.7 2.1.8
2.1.8.1
Interrupt Table Register (INTB) Program Counter (PC) Flag Register (FLG)
Carry Flag (C)
INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table.
PC is 24 bits wide and indicates the address of the next instruction to be executed.
FLG is a 16-bit register indicating the CPU state.
The C flag indicates whether or not carry or borrow has been generated after executing an instruction.
2.1.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.1.8.3
Zero Flag (Z)
The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0.
2.1.8.4
Sign Flag (S)
The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0.
2.1.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1.
2.1.8.6
Overflow Flag (O)
The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
2. Central Processing Unit (CPU)
2.1.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when an interrupt request is acknowledged.
2.1.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1. The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction specifying software interrupt numbers 0 to 31 is executed.
2.1.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority level than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
Only write 0 to bits assigned to the reserved space. When read, the bits return undefined values.
2.2
High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows: * Flag save register (SVF) * PC save register (SVP) * Vector register (VCT)
2.3
DMAC-Associated Registers
Registers associated with the DMAC are as follows: * DMA mode register (DMD0, DMD1) * DMA transfer count register (DCT0, DCT1) * DMA transfer count reload register (DRC0, DRC1) * DMA memory address register (DMA0, DMA1) * DMA memory address reload register (DRA0, DRA1) * DMA SFR address register (DSA0, DSA1)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
3. Memory
3.
Memory
Figure 3.1 shows a memory map of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has 16-Mbyte address space from addresses 000000h to FFFFFFh. The internal ROM is allocated in lower addresses, beginning with address FFFFFFh. For example, a 512-Kbyte internal ROM area is allocated in addresses F80000h to FFFFFFh. The fixed interrupt vectors are allocated in addresses FFFFDCh to FFFFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses, beginning with address 000400h. For example, a 48-Kbyte internal RAM area is allocated in addresses 000400h to 00C3FFh. The internal RAM is used not only for storing data but for the stacks when subroutines are called or when interrupt requests are acknowledged. SFRs are allocated in addresses 000000h to 0003FFh. The peripheral function control registers such as for I/O ports, A/D converters, serial interfaces, timers are allocated here. All blank spaces within SFRs are reserved and cannot be accessed by users. The special page vectors are allocated addresses FFFE00h to FFFFDBh. They are used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
000000h SFR 000400h Internal RAM Capacity 24 Kbytes 31 Kbytes 48 Kbytes XXXXXXh 0063FFh 007FFFh 00C3FFh XXXXXXh Reserved 00F000h 00FFFFh Internal ROM(3) (Data space) External space(1) Internal ROM Capacity 384 Kbytes 512 Kbytes 768 Kbytes 1024 Kbytes YYYYYYh FA0000h F80000h F40000h F00000h FFFFFFh F00000h YYYYYYh Internal ROM(4) FFFFFFh NMI Reset Reserved(2)
Watchdog timer (5)
Internal RAM
FFFE00h
Special page vector table
Undefined instruction
FFFFDCh
Overflow BRK instruction Address match
NOTES: 1. The space is used as the external space in memory expansion mode and in microprocessor mode. It is reserved in single-ship mode. 2. The space is reserved in memory expansion mode. It is used as the external space in microprocessor mode. 3. Additional 4-Kbyte space is provided in the flash memory version to store data. This space is used in single-chip mode and memory expansion mode. It is reserved in microprocessor mode. 4. This space is used in single-chip mode and memory expansion mode. It is used as the external space in microprocessor mode. 5. The watchdog timer interrupt, oscillation stop detection interrupt, and Vdet4 detection interrupt use the same vector.
Figure 3.1
Memory Map
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
Special Function Registers (SFRs) are the control registers of peripheral functions. Tables 4.1 to 4.20 list SFR address maps. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh Vdet4 Detection Interrupt Register D4INT XX00 0000b Address Match Interrupt Register 5 RMAD5 000000h Address Match Interrupt Register 4 RMAD4 000000h PLL Control Register 0 PLL Control Register 1 PLC0 PLC1 0001 X010b 000X 0000b Address Match Interrupt Register 3 RMAD3 000000h Voltage Detection Register 1 VCR1 0000 1000b Address Match Interrupt Register 2 RMAD2 000000h Voltage Detection Register 2 VCR2 00h Address Match Interrupt Register 1 RMAD1 000000h Processor Mode Register 2 PM2 00h Address Match Interrupt Register 0 RMAD0 000000h Address Match Interrupt Enable Register Protect Register External Data Bus Width Control Register Main Clock Division Register Oscillation Stop Detection Register Watchdog Timer Start Register Watchdog Timer Control Register AIER PRCR DS MCD CM2 WDTS WDC 00h XXXX 0000b XXXX 1000b(BYTE="L") XXXX 0000b(BYTE="H") XXX0 1000b 00h XXh 00XX XXXXb Processor Mode Register 0(1) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 1000 0000b(CNVSS="L") 0000 0011b(CNVSS="H") 00h 0000 1000b 0010 0000b
SFR Address Map (1/20)
Register Symbol After Reset
X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. Bits PM01 and PM00 in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has been performed.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.2
Address 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh X: Undefined Blank spaces are all reserved. No access is allowed. Flash Memory Control Register 0 Flash Memory Control Register 1 External Space Wait Control Register 0 External Space Wait Control Register 1 External Space Wait Control Register 2 External Space Wait Control Register 3 Address Match Interrupt Register 7 Address Match Interrupt Register 6
4. Special Function Registers (SFRs)
SFR Address Map (2/20)
Register Symbol After Reset
RMAD6
000000h
RMAD7
000000h
EWCR0 EWCR1 EWCR2 EWCR3
X0X0 0011b X0X0 0011b X0X0 0011b X0X0 0011b
FMR1
0000 0X0Xb 0000 0001b(Flash Memory) XXXX XXX0b(Mask ROM)
FMR0
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.3
Address 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh DMA1 Interrupt Control Register UART2 Transmit/NACK Interrupt Control Register DMA3 Interrupt Control Register UART3 Transmit/NACK Interrupt Control Register Timer A1 Interrupt Control Register UART4 Transmit/NACK Interrupt Control Register Timer A3 Interrupt Control Register UART2 Bus Conflict Detection Interrupt Control Register II/O Interrupt Control Register 11 / CAN0 Interrupt Control Register 2 DMA0 Interrupt Control Register Timer B5 Interrupt Control Register DMA2 Interrupt Control Register UART2 Receive/ACK Interrupt Control Register Timer A0 Interrupt Control Register UART3 Receive/ACK Interrupt Control Register Timer A2 Interrupt Control Register UART4 Receive/ACK Interrupt Control Register Timer A4 Interrupt Control Register UART0/UART3 Bus Conflict Detection Interrupt Control Register UART0 Receive/ACK Interrupt Control Register A/D0 Conversion Interrupt Control Register UART1 Receive/ACK Interrupt Control Register II/O Interrupt Control Register 0 / CAN1 interrupt Control Register 0 Timer B1 Interrupt Control Register II/O Interrupt Control Register 2 Timer B3 Interrupt Control Register II/O Interrupt Control Register 4 INT5 Interrupt Control Register II/O Interrupt Control Register 6 INT3 Interrupt Control Register II/O Interrupt Control Register 8 INT1 Interrupt Control Register II/O Interrupt Control Register 10 / CAN0 Interrupt Control Register 1
4. Special Function Registers (SFRs)
SFR Address Map (3/20)
Register Symbol After Reset
DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/BCN3IC S0RIC AD0IC S1RIC IIO0IC/CAN3IC TB1IC IIO2IC TB3IC IIO4IC INT5IC IIO6IC INT3IC IIO8IC INT1IC IIO10IC/CAN1IC IIO11IC/CAN2IC
XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XXXX X000b XXXX X000b
DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC
XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b
X: Undefined Blank spaces are all reserved. No access is allowed.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.4
Address 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh to 00DFh X: Undefined Blank spaces are all reserved. No access is allowed. Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Enable Register 4 Interrupt Enable Register 5 Interrupt Enable Register 6 Interrupt Enable Register 7 Interrupt Enable Register 8 Interrupt Enable Register 9 Interrupt Enable Register 10 Interrupt Enable Register 11
4. Special Function Registers (SFRs)
SFR Address Map (4/20)
Register UART0 Transmit/NACK Interrupt Control Register UART1/UART4 Bus Conflict Detection Interrupt Control Register UART1 Transmit/NACK Interrupt Control Register Key Input Interrupt Control Register Timer B0 Interrupt Control Register II/O Interrupt Control Register 1 / CAN1 Interrupt Control Register 1 Timer B2 Interrupt Control Register II/O Interrupt Control Register 3 Timer B4 Interrupt Control Register II/O Interrupt Control Register 5 /CAN1 Interrupt Control Register 2 INT4 Interrupt Control Register II/O Interrupt Control Register 7 INT2 Interrupt Control Register II/O Interrupt Control Register 9 / CAN0 Interrupt Control Register 0 INT0 Interrupt Control Register Exit Priority Register Interrupt Request Register 0 Interrupt Request Register 1 Interrupt Request Register 2 Interrupt Request Register 3 Interrupt Request Register 4 Interrupt Request Register 5 Interrupt Request Register 6 Interrupt Request Register 7 Interrupt Request Register 8 Interrupt Request Register 9 Interrupt Request Register 10 Interrupt Request Register 11 S0TIC BCN1IC/BCN4IC S1TIC KUPIC TB0IC IIO1IC/CAN4IC TB2IC IIO3IC TB4IC IIO5IC/CAN5IC INT4IC IIO7IC INT2IC IIO9IC/CAN0IC INT0IC RLVL IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Symbol After Reset XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XXXX 0000b 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb
IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 30 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.5
Address 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h Group 0 Receive CRC Code Register Group 0 Transmit CRC Code Register Group 0 SI/O Expansion Mode Register Group 0 SI/O Extended Receive Control Register Group 0 SI/O Special Communication Interrupt Detection Register Group 0 SI/O Extended Transmit Control Register Group 1 Time Measurement/Waveform Generation Register 0 Group 1 Time Measurement/Waveform Generation Register 1 Group 1 Time Measurement/Waveform Generation Register 2 Group 1 Time Measurement/Waveform Generation Register 3 Group 1 Time Measurement/Waveform Generation Register 4 Group 1 Time Measurement/Waveform Generation Register 5 Group 1 Time Measurement/Waveform Generation Register 6 Group 1 Time Measurement/Waveform Generation Register 7 Group 1 Waveform Generation Control Register 0 Group 1 Waveform Generation Control Register 1 Group 1 Waveform Generation Control Register 2 Group 1 Waveform Generation Control Register 3 Group 1 Waveform Generation Control Register 4 Group 1 Waveform Generation Control Register 5 Group 1 Waveform Generation Control Register 6 Group 1 Waveform Generation Control Register 7 Group 1 Time Measurement Control Register 0 Group 1 Time Measurement Control Register 1 Group 0 Receive Input Register Group 0 SI/O Communication Mode Register Group 0 Transmit Output Register Group 0 SI/O Communication Control Register Group 0 Data Compare Register 0 Group 0 Data Compare Register 1 Group 0 Data Compare Register 2 Group 0 Data Compare Register 3 Group 0 Data Mask Register 0 Group 0 Data Mask Register 1 Communication Clock Select Register Group 0 SI/O Receive Buffer Register Group 0 Transmit Buffer/Receive Data Register
4. Special Function Registers (SFRs)
SFR Address Map (5/20)
Register Symbol After Reset
G0RB G0TB/G0DR G0RI G0MR G0TO G0CR G0CMP0 G0CMP1 G0CMP2 G0CMP3 G0MSK0 G0MSK1 CCS
XXXX XXXXb XXX0 XXXXb XXh XXh 00h XXh 0000 X011b XXh XXh XXh XXh XXh XXh XXXX 0000b
G0RCRC G0TCRC G0EMR G0ERC G0IRF G0ETC G1TM0/G1PO0 G1TM1/G1PO1 G1TM2/G1PO2 G1TM3/G1PO3 G1TM4/G1PO4 G1TM5/G1PO5 G1TM6/G1PO6 G1TM7/G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1
XXXXh 0000h 00h 00h 0000 XXXXb 0000 0XXXb XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0000 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 00h 00h
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 31 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.6
Address 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh Group 1 Receive CRC Code Register Group 1 Transmit CRC Code Register Group 1 SI/O Expansion Mode Register Group 1 SI/O Extended Receive Control Register Group 1 SI/O Special Communication Interrupt Detection Register Group 1 SI/O Extended Transmit Control Register Group 2 Waveform Generation Register 0 Group 2 Waveform Generation Register 1 Group 2 Waveform Generation Register 2 Group 2 Waveform Generation Register 3 Group 2 Waveform Generation Register 4 Group 2 Waveform Generation Register 5 Group 2 Waveform Generation Register 6 Group 2 Waveform Generation Register 7 Group 1 Receive Input Register Group 1 SI/O Communication Mode Register Group 1 Transmit Output Register Group 1 SI/O Communication Control Register Group 1 Data Compare Register 0 Group 1 Data Compare Register 1 Group 1 Data Compare Register 2 Group 1 Data Compare Register 3 Group 1 Data Mask Register 0 Group 1 Data Mask Register 1
4. Special Function Registers (SFRs)
SFR Address Map (6/20)
Register Group 1 Time Measurement Control Register 2 Group 1 Time Measurement Control Register 3 Group 1 Time Measurement Control Register 4 Group 1 Time Measurement Control Register 5 Group 1 Time Measurement Control Register 6 Group 1 Time Measurement Control Register 7 Group 1 Base Timer Register Group 1 Base Timer Control Register 0 Group 1 Base Timer Control Register 1 Group 1 Time Measurement Prescaler Register 6 Group 1 Time Measurement Prescaler Register 7 Group 1 Function Enable Register Group 1 Function Select Register Group 1 SI/O Receive Buffer Register Group 1 Transmit Buffer/Receive Data Register Symbol G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1RB G1TB/G1DR G1RI G1MR G1TO G1CR G1CMP0 G1CMP1 G1CMP2 G1CMP3 G1MSK0 G1MSK1 00h 00h 00h 00h 00h 00h XXXXh 00h X000 000Xb 00h 00h 00h 00h XXXX XXXXb X000 XXXXb XXh XXh 00h XXh 0000 X011b XXh XXh XXh XXh XXh XXh After Reset
G1RCRC G1TCRC G1EMR G1ERC G1IRF G1ETC G2PO0 G2PO1 G2PO2 G2PO3 G2PO4 G2PO5 G2PO6 G2PO7
XXXXh 0000h 00h 00h 0000 XXXXb 0000 0XXXb XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 32 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.7
Address 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh to 01BFh X: Undefined Blank spaces are all reserved. No access is allowed. Input Function Select Register B Input Function Select Register Input Function Select Register A Group 2 SI/O Communication Mode Register Group 2 SI/O Communication Control Register Group 2 SI/O Transmit Buffer Register Group 2 SI/O Receive Buffer Register Group 2 IEBus Address Register Group 2 IEBus Control Register Group 2 IEBus Transmit Interrupt Source Detection Register Group 2 IEBus Receive Interrupt Source Detection Register Group 2 Function Enable Register Group 2 RTP Output Buffer Register Group 2 Base Timer Register Group 2 Base Timer Control Register 0 Group 2 Base Timer Control Register 1 Base Timer Start Register
4. Special Function Registers (SFRs)
SFR Address Map (7/20)
Register Group 2 Waveform Generation Control Register 0 Group 2 Waveform Generation Control Register 1 Group 2 Waveform Generation Control Register 2 Group 2 Waveform Generation Control Register 3 Group 2 Waveform Generation Control Register 4 Group 2 Waveform Generation Control Register 5 Group 2 Waveform Generation Control Register 6 Group 2 Waveform Generation Control Register 7 Symbol G2POCR0 G2POCR1 G2POCR2 G2POCR3 G2POCR4 G2POCR5 G2POCR6 G2POCR7 00h 00h 00h 00h 00h 00h 00h 00h After Reset
G2BT G2BCR0 G2BCR1 BTSR G2FE G2RTP
XXXXh 00h 00h XXXX 0000b 00h 00h
G2MR G2CR G2TB G2RB IEAR IECR IETIF IERIF
00XX X000b 0000 X000b XXXXh XXXXh XXXXh 00XX X000b XXX0 0000b XXX0 0000b
IPSB IPS IPSA
00h 00h 00h
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 33 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.8
Address 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh CAN0 Message Slot Buffer 0 Standard ID0(1)(2) CAN0 Message Slot Buffer 0 Standard ID1(1)(2) CAN0 Message Slot Buffer 0 Extended ID0(1)(2) CAN0 Message Slot Buffer 0 Extended ID1(1)(2) CAN0 Message Slot Buffer 0 Extended ID2(1)(2) CAN0 Message Slot Buffer 0 Data Length Code(1)(2) CAN0 Message Slot Buffer 0 Data 0(1)(2) CAN0 Message Slot Buffer 0 Data 1(1)(2) CAN0 Message Slot Buffer 0 Data 2(1)(2) CAN0 Message Slot Buffer 0 Data 3(1)(2) CAN0 Message Slot Buffer 0 Data 4(1)(2) CAN0 Message Slot Buffer 0 Data 5(1)(2) CAN0 Message Slot Buffer 0 Data 6(1)(2) CAN0 Message Slot Buffer 0 Data 7(1)(2) CAN0 Message Slot Buffer 0 Time Stamp High-Order(1)(2) CAN0 Message Slot Buffer 0 Time Stamp Low-Order(1)(2) RTP Output Buffer Register 0 RTP Output Buffer Register 1 RTP Output Buffer Register 2 RTP Output Buffer Register 3 UART5 Baud Rate Register UART5 Transmit Buffer Register UART5 Transmit/Receive Control Register 0 UART5 Transmit/Receive Control Register 1 UART5 Receive Buffer Register UART6 Transmit/Receive Mode Register UART6 Baud Rate Register UART6 Transmit Buffer Register UART6 Transmit/Receive Control Register 0 UART6 Transmit/Receive Control Register 1 UART6 Receive Buffer Register UART5, UART6 Transmit/Receive Control Register UART5, UART6 Input Pin Function Select Register
4. Special Function Registers (SFRs)
SFR Address Map (8/20)
Register UART5 Transmit/Receive Mode Register U5MR U5BRG U5TB U5C0 U5C1 U5RB U6MR U6BRG U6TB U6C0 U6C1 U6RB U56CON U56IS Symbol 00h XXh XXXXh 0000 1000b XXXX 0010b XXXXh 00h XXh XXXXh 0000 1000b XXXX 0010b XXXXh X000 0000b X000 X000b After Reset
RTP0R RTP1R RTP2R RTP3R
XXh XXh XXh XXh
C0SLOT0_0 C0SLOT0_1 C0SLOT0_2 C0SLOT0_3 C0SLOT0_4 C0SLOT0_5 C0SLOT0_6 C0SLOT0_7 C0SLOT0_8 C0SLOT0_9 C0SLOT0_10 C0SLOT0_11 C0SLOT0_12 C0SLOT0_13 C0SLOT0_14 C0SLOT0_15
XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 2. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 34 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.9
Address 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh CAN0 Mode Register CAN0 Error Interrupt Mask Register CAN0 Error Interrupt Status Register CAN0 Error Source Register CAN0 Baud Rate Prescaler CAN0 Slot Interrupt Mask Register
4. Special Function Registers (SFRs)
SFR Address Map (9/20)
Register(2)(3) CAN0 Message Slot Buffer 1 Standard ID0 CAN0 Message Slot Buffer 1 Standard ID1 CAN0 Message Slot Buffer 1 Extended ID0 CAN0 Message Slot Buffer 1 Extended ID1 CAN0 Message Slot Buffer 1 Extended ID2 CAN0 Message Slot Buffer 1 Data Length Code CAN0 Message Slot Buffer 1 Data 0 CAN0 Message Slot Buffer 1 Data 1 CAN0 Message Slot Buffer 1 Data 2 CAN0 Message Slot Buffer 1 Data 3 CAN0 Message Slot Buffer 1 Data 4 CAN0 Message Slot Buffer 1 Data 5 CAN0 Message Slot Buffer 1 Data 6 CAN0 Message Slot Buffer 1 Data 7 CAN0 Message Slot Buffer 1 Time Stamp High-Order CAN0 Message Slot Buffer 1 Time Stamp Low-Order CAN0 Control Register 0 CAN0 Status Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Time Stamp Register CAN0 Transmit Error Count Register CAN0 Receive Error Count Register CAN0 Slot Interrupt Status Register Symbol C0SLOT1_0 C0SLOT1_1 C0SLOT1_2 C0SLOT1_3 C0SLOT1_4 C0SLOT1_5 C0SLOT1_6 C0SLOT1_7 C0SLOT1_8 C0SLOT1_9 C0SLOT1_10 C0SLOT1_11 C0SLOT1_12 C0SLOT1_13 C0SLOT1_14 C0SLOT1_15 C0CTLR0 C0STR C0IDR C0CONR C0TSR C0TEC C0REC C0SISTR XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XX01 0X01b(1) XXXX 0000b(1) 0000 0000b(1) X000 0X01b(1) 0000h(1) 0000 XXXXb(1) 0000 0000b(1) 0000h(1) 00h(1) 00h(1) 0000h(1) After Reset
C0SIMKR
0000h(1)
C0EIMKR C0EISTR C0EFR C0BRP C0MDR
XXXX X000b(1) XXXX X000b(1) 00h(1) 0000 0001b(1) XXXX XX00b(1)
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 2. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 3. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 35 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.10
Address 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah to 024Fh CAN0 Acceptance Filter Support Register CAN0 Message Slot 0 Control Register / CAN0 Local Mask Register A Standard ID0 CAN0 Message Slot 1 Control Register / CAN0 Local Mask Register A Standard ID1 CAN0 Message Slot 2 Control Register / CAN0 Local Mask Register A Extended ID0 CAN0 Message Slot 3 Control Register / CAN0 Local Mask Register A Extended ID1 CAN0 Message Slot 4 Control Register / CAN0 Local Mask Register A Extended ID2 CAN0 Message Slot 5 Control Register CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register CAN0 Message Slot 8 Control Register / CAN0 Local Mask Register B Standard ID0 CAN0 Message Slot 9 Control Register / CAN0 Local Mask Register B Standard ID1 CAN0 Message Slot 10 Control Register / CAN0 Local Mask Register B Extended ID0 CAN0 Message Slot 11 Control Register / CAN0 Local Mask Register B Extended ID1 CAN0 Message Slot 12 Control Register / CAN0 Local Mask Register B Extended ID2 CAN0 Message Slot 13 Control Register CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register CAN0 Slot Buffer Select Register CAN0 Control Register 1 CAN0 Sleep Control Register CAN0 Global Mask Register Standard ID0 CAN0 Global Mask Register Standard ID1 CAN0 Global Mask Register Extended ID0 CAN0 Global Mask Register Extended ID1 CAN0 Global Mask Register Extended ID2 CAN0 Single Shot Status Register CAN0 Single Shot Control Register
4. Special Function Registers (SFRs)
SFR Address Map (10/20)
Register(3)(4) Symbol C0SSCTLR After Reset 0000h(1)(2)
C0SSSTR
0000h(1)(2)
C0GMR0 C0GMR1 C0GMR2 C0GMR3 C0GMR4
XXX0 0000b(1)(2) XX00 0000b(1)(2) XXXX 0000b(1)(2) 00h(1)(2) XX00 0000b(1)(2)
C0MCTL0 / C0LMAR0 C0MCTL1 / C0LMAR1 C0MCTL2 / C0LMAR2 C0MCTL3 / C0LMAR3 C0MCTL4 / C0LMAR4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 / C0LMBR0 C0MCTL9 / C0LMBR1 C0MCTL10 / C0LMBR2 C0MCTL11 / C0LMBR3 C0MCTL12 / C0LMBR4 C0MCTL13 C0MCTL14 C0MCTL15 C0SBS C0CTLR1 C0SLPR
0000 0000b(1)(2)/ XXX0 0000b(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 0000 0000b(1)(2)/ XXXX 0000b(1)(2) 00h(1)(2)/ 00h(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 00h(1)(2) 00h(1)(2) 00h(1)(2) 0000 0000b(1)(2)/ XXX0 0000b(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 0000 0000b(1)(2)/ XXXX 0000b(1)(2) 00h(1)(2)/ 00h(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 00h(1)(2) 00h(1)(2) 00h(1)(2) 00h(2) X000 00XXb(2) XXXX XXX0b 0000 0000b(2) 0000 0001b(2)
C0AFS
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register can switch functions for addresses 0220h to 023Fh. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 3. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 4. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 36 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.11
Address 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh CAN1 Message Slot Buffer 0 Standard ID0 CAN1 Message Slot Buffer 0 Standard ID1 CAN1 Message Slot Buffer 0 Extended ID0 CAN1 Message Slot Buffer 0 Extended ID1 CAN1 Message Slot Buffer 0 Extended ID2 CAN1 Message Slot Buffer 0 Data Length Code CAN1 Message Slot Buffer 0 Data 0 CAN1 Message Slot Buffer 0 Data 1 CAN1 Message Slot Buffer 0 Data 2 CAN1 Message Slot Buffer 0 Data 3 CAN1 Message Slot Buffer 0 Data 4 CAN1 Message Slot Buffer 0 Data 5 CAN1 Message Slot Buffer 0 Data 6 CAN1 Message Slot Buffer 0 Data 7 CAN1 Message Slot Buffer 0 Time Stamp High-Order CAN1 Message Slot Buffer 0 Time Stamp Low-Order CAN1 Message Slot Buffer 1 Standard ID0 CAN1 Message Slot Buffer 1 Standard ID1 CAN1 Message Slot Buffer 1 Extended ID0 CAN1 Message Slot Buffer 1 Extended ID1 CAN1 Message Slot Buffer 1 Extended ID2 CAN1 Message Slot Buffer 1 Data Length Code CAN1 Message Slot Buffer 1 Data 0 CAN1 Message Slot Buffer 1 Data 1 CAN1 Message Slot Buffer 1 Data 2 CAN1 Message Slot Buffer 1 Data 3 CAN1 Message Slot Buffer 1 Data 4 CAN1 Message Slot Buffer 1 Data 5 CAN1 Message Slot Buffer 1 Data 6 CAN1 Message Slot Buffer 1 Data 7 CAN1 Message Slot Buffer 1 Time Stamp High-Order CAN1 Message Slot Buffer 1 Time Stamp Low-Order CAN1 Acceptance Filter Support Register CAN1 Slot Buffer Select Register CAN1 Control Register 1 CAN1 Sleep Control Register
4. Special Function Registers (SFRs)
SFR Address Map (11/20)
Register(2)(3) Symbol C1SBS C1CTLR1 C1SLPR 00h(1) X000 00XXb(1) XXXX XXX0b(1) 0000 0000b(1) 0000 0001b(1) After Reset
C1AFS
C1SLOT0_0 C1SLOT0_1 C1SLOT0_2 C1SLOT0_3 C1SLOT0_4 C1SLOT0_5 C1SLOT0_6 C1SLOT0_7 C1SLOT0_8 C1SLOT0_9 C1SLOT0_10 C1SLOT0_11 C1SLOT0_12 C1SLOT0_13 C1SLOT0_14 C1SLOT0_15 C1SLOT1_0 C1SLOT1_1 C1SLOT1_2 C1SLOT1_3 C1SLOT1_4 C1SLOT1_5 C1SLOT1_6 C1SLOT1_7 C1SLOT1_8 C1SLOT1_9 C1SLOT1_10 C1SLOT1_11 C1SLOT1_12 C1SLOT1_13 C1SLOT1_14 C1SLOT1_15
XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 2. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 3. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 37 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.12
Address 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh CAN1 Global Mask Register Standard ID0 CAN1 Global Mask Register Standard ID1 CAN1 Global Mask Register Extended ID0 CAN1 Global Mask Register Extended ID1 CAN1 Global Mask Register Extended ID2 CAN1 Single Shot Status Register CAN1 Single Shot Control Register CAN1 Mode Register CAN1 Error Interrupt Mask Register CAN1 Error Interrupt Status Register CAN1 Error Source Register CAN1 Baud Rate Prescaler CAN1 Slot Interrupt Mask Register CAN1 Control Register 0 CAN1 Status Register CAN1 Extended ID Register CAN1 Configuration Register CAN1 Time Stamp Register CAN1 Transmit Error Count Register CAN1 Receive Error Count Register CAN1 Slot Interrupt Status Register
4. Special Function Registers (SFRs)
SFR Address Map (12/20)
Register(3)(4) Symbol C1CTLR0 C1STR C1IDR C1CONR C1TSR C1TEC C1REC C1SISTR After Reset XX01 0X01b(2) XXXX 0000b(2) 0000 0000b(2) X000 0X01b(2) 0000h(2) 0000 XXXXb(2) 0000 0000b(2) 0000h(2) 00h(2) 00h(2) 0000h(2)
C1SIMKR
0000h(2)
C1EIMKR C1EISTR C1EFR C1BRP C1MDR
XXXX X000b(2) XXXX X000b(2) 00h(2) 0000 0001b(2) XXXX XX00b(2)
C1SSCTLR
0000h(1)(2)
C1SSSTR
0000h(1)(2)
C1GMR0 C1GMR1 C1GMR2 C1GMR3 C1GMR4
XXX0 0000b(1)(2) XX00 0000b(1)(2) XXXX 0000b(1)(2) 00h(1)(2) XX00 0000b(1)(2)
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register can switch functions for addresses 02A0h to 02BFh. 2. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 3. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 4. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 38 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.13
Address 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh
4. Special Function Registers (SFRs)
SFR Address Map (13/20)
Register(3)(4) Symbol C1MCTL0 / C1LMAR0 C1MCTL1 / C1LMAR1 C1MCTL2 / C1LMAR2 C1MCTL3 / C1LMAR3 C1MCTL4 / C1LMAR4 C1MCTL5 C1MCTL6 C1MCTL7 C1MCTL8 / C1LMBR0 C1MCTL9 / C1LMBR1 C1MCTL10 / C1LMBR2 C1MCTL11 / C1LMBR3 C1MCTL12 / C1LMBR4 C1MCTL13 C1MCTL14 C1MCTL15 After Reset 0000 0000b(1)(2)/ XXX0 0000b(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 0000 0000b(1)(2)/ XXXX 0000b(1)(2) 00h(1)(2)/ 00h(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 00h(1)(2) 00h(1)(2) 00h(1)(2) 0000 0000b(1)(2)/ XXX0 0000b(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 0000 0000b(1)(2)/ XXXX 0000b(1)(2) 00h(1)(2)/ 00h(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 00h(1)(2) 00h(1)(2) 00h(1)(2)
CAN1 Message Slot 0 Control Register / CAN1 Local Mask Register A Standard ID0 CAN1 Message Slot 1 Control Register / CAN1 Local Mask Register A Standard ID1 CAN1 Message Slot 2 Control Register / CAN1 Local Mask Register A Extended ID0 CAN1 Message Slot 3 Control Register / CAN1 Local Mask Register A Extended ID1 CAN1 Message Slot 4 Control Register / CAN1 Local Mask Register A Extended ID2 CAN1 Message Slot 5 Control Register CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register CAN1 Message Slot 8 Control Register / CAN1 Local Mask Register B Standard ID0 CAN1 Message Slot 9 Control Register / CAN1 Local Mask Register B Standard ID1 CAN1 Message Slot 10 Control Register / CAN1 Local Mask Register B Extended ID0 CAN1 Message Slot 11 Control Register / CAN1 Local Mask Register B Extended ID1 CAN1 Message Slot 12 Control Register / CAN1 Local Mask Register B Extended ID2 CAN1 Message Slot 13 Control Register CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C1CTLR1 register can switch functions for addresses 02A0h to 02BFh. 2. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 3. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 4. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 39 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.14
Address 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Baud Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register X0 Register, Y0 Register X1 Register, Y1 Register X2 Register, Y2 Register X3 Register, Y3 Register X4 Register, Y4 Register X5 Register, Y5 Register X6 Register, Y6 Register X7 Register, Y7 Register X8 Register, Y8 Register X9 Register, Y9 Register X10 Register, Y10 Register X11 Register, Y11 Register X12 Register, Y12 Register X13 Register, Y13 Register X14 Register, Y14 Register X15 Register, Y15 Register X/Y Control Register
4. Special Function Registers (SFRs)
SFR Address Map (14/20)
Register Symbol
X0R, Y0R XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh
After Reset
X1R, Y1R X2R, Y2R X3R, Y3R X4R, Y4R X5R, Y5R X6R, Y6R X7R, Y7R X8R, Y8R X9R, Y9R X10R, Y10R X11R, Y11R X12R, Y12R X13R, Y13R X14R, Y14R X15R, Y15R XYC
XXXX XX00b
U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 40 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.15
Address 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register External Interrupt Source Select Register 1(1) External Interrupt Source Select Register Timer B3 Register Timer B4 Register Timer B5 Register Timer A11 Register Timer A21 Register Timer A41 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter UART4 Special Mode Register 4 UART4 Special Mode Register 3 UART4 Special Mode Register 2 UART4 Special Mode Register UART4 Transmit/Receive Mode Register UART4 Baud Rate Register UART4 Transmit Buffer Register UART4 Transmit/Receive Control Register 0 UART4 Transmit/Receive Control Register 1 UART4 Receive Buffer Register Timer B3, B4, B5 Count Start Register
4. Special Function Registers (SFRs)
SFR Address Map (15/20)
Register Symbol After Reset
U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 000X XXXXb
TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
XXXXh XXXXh XXXXh 00h 00h XX11 1111b XX11 1111b XXh XXh
TB3 TB4 TB5
XXXXh XXXXh XXXXh
TB3MR TB4MR TB5MR IFSRA IFSR
00XX 0000b 00XX 0000b 00XX 0000b 00h 00h
X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. The IFSRA register is included in the 144-pin package only.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 41 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.16
Address 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 044Ch 034Dh 034Eh 034Fh Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Baud Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Count Start Register Clock Prescaler Reset Register One-Shot Start Register Trigger Select Register Up/Down Select Register UART3 Special Mode Register 4 UART3 Special Mode Register 3 UART3 Special Mode Register 2 UART3 Special Mode Register UART3 Transmit/Receive Mode Register UART3 Baud Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register
4. Special Function Registers (SFRs)
SFR Address Map (16/20)
Register Symbol After Reset
U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 00h 0XXX XXXXb 00h 00h 00h
TA0 TA1 TA2 TA3 TA4
XXXXh XXXXh XXXXh XXXXh XXXXh
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 42 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.17
Address 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh DMA0 Request Source Select Register DMA1 Request Source Select Register DMA2 Request Source Select Register DMA3 Request Source Select Register CRC Data Register CRC Input Register IrDA Control Register UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Baud Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register Count Source Prescaler Register(1)
4. Special Function Registers (SFRs)
SFR Address Map (17/20)
Register TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR Symbol After Reset XXXXh XXXXh XXXXh 00h 00h 00h 00h 00h 00XX 0000b 00XX 0000b 00XX 0000b XXXX XXX0b 0XXX 0000b
U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
IRCON
X000 0000b
DM0SL DM1SL DM2SL DM3SL CRCD CRCIN
0X00 0000b 0X00 0000b 0X00 0000b 0X00 0000b XXXXh XXh
X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 43 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.18
Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh X: Undefined Blank spaces are all reserved. No access is allowed. D/A Control Register D/A Control Register 1 D/A Register 1 A/D0 Control Register 2 A/D0 Control Register 3 A/D0 Control Register 0 A/D0 Control Register 1 D/A Register 0 A/D0 Control Register 4 A/D0 Register 0 A/D0 Register 1 A/D0 Register 2 A/D0 Register 3 A/D0 Register 4 A/D0 Register 5 A/D0 Register 6 A/D0 Register 7
4. Special Function Registers (SFRs)
SFR Address Map (18/20)
Register AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 Symbol 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh After Reset
AD0CON4 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON DACON1
XXXX 00XXb XX0X X000b XXXX X000b 00h 00h XXh XXh XXXX XX00b XXXX 0000b
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 44 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.19
Address 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh Function Select Register B5(1) Function Select Register A6(1) Function Select Register A7(1) Function Select Register B6(1) Function Select Register B7(1) Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register(1) Port P10 Direction Register Port P11 Direction Register(1)(2) Port P12 Register(1) Port P13 Register(1) Port P12 Direction Register(1)(2) Port P13 Direction Register(1)(2) Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3 Function Select Register A4 Function Select Register A5(1) Function Select Register C6(1) Function Select Register E1 Function Select Register C2 Function Select Register C3 Function Select Register D1 Function Select Register D2 Function Select Register B9(1) Function Select Register E2 Function Select Register A8(1) Function Select Register A9(1)
4. Special Function Registers (SFRs)
SFR Address Map (19/20)
Register PS8 PS9 PSL9 PSE2 Symbol 00h XXX0 XX00b XXXX XX0Xb After Reset X000 0000b
PSD1 PSD2 PSC6 PSE1 PSC2 PSC3 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 PS4 PS5 PSL5 PS6 PS7 PSL6 PSL7 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13
00X0 XX00b XXXX XX0Xb XXXX 0X00b 00XX XX00b XXXX X00Xb X0XX XXXXb 00h 00h 00h 00h 00h 00X0 0000b 00h 00X0 0000b 00h 00h XXX0 0000b XXX0 0000b 00h 00h 00h 00h XXh XXh 00h 00h XXh XXh 00X0 0000b 00h XXh XXh 00h XXX0 0000b XXh XXh 00h 00h
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. These registers cannot be used in the 100-pin package. 2. Set to FFh in the 100-pin package.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 45 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.20
Address 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh Port Control Register Pull-Up Control Register 0 Pull-Up Control Register 1 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Pull-Up Control Register 2 Pull-Up Control Register 3 Pull-Up Control Register 4(1)(3) Port P14 Register(1) Port P15 Register(1) Port P14 Direction Register(1)(2) Port P15 Direction Register(1)(2)
4. Special Function Registers (SFRs)
SFR Address Map (20/20)
Register P14 P15 PD14 PD15 Symbol XXh XXh X000 0000b 00h After Reset
PUR2 PUR3 PUR4
00h 00h XXXX 0000b
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5
XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h
PUR0 PUR1
00h XXXX 0000b
PCR
XXXX X000b
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. These registers cannot be used in the 100-pin package. 2. Set to FFh in the 100-pin package. 3. Set to 00h in the 100-pin package.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 46 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
5.
Electrical Characteristics
Table 5.1
Symbol VCC1, VCC2 VCC2 AVCC VI Supply voltage Supply voltage Analog supply voltage Input voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1), VREF, XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P7_0, P7_1 VO Output voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P14_0 to 14_6, P15_0 to P15_7(1), XOUT P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P7_0, P7_1 Pd Topr Power consumption Operating ambient temperature during CPU operation during programming or erasing Flash memory -40CTopr85C
Absolute Maximum Ratings
Parameter Condition VCC1 = AVCC - VCC1 = AVCC Value -0.3 to 6.0 -0.3 to VCC1 + 0.1 -0.3 to 6.0 -0.3 to VCC1 + 0.3 Unit V V V V
-0.3 to VCC2 + 0.3
-0.3 to 6.0 -0.3 to VCC1 + 0.3 V
-0.3 to VCC2 + 0.3
-0.3 to 6.0 500 -20 to 85/ -40 to 85(2) 0 to 60 -65 to 150 mW C C C
Tstg
Storage temperature
NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. Contact a Renesas sales office if temperature range of -40 to 85C is required.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 47 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions (1/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified)
Parameter Supply voltage (VCC1 VCC2) Analog supply voltage Supply voltage Analog supply voltage 0.8VCC2 Input high "H" P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(2) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7(1), 0.8VCC1 P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(2), XIN, RESET, CNVSS, BYTE P7_0, P7_1 P0_0 to P0_7, P1_0 to P1_7 (in memory expansion mode and microprocessor mode) 0.8VCC1 0.5VCC2 P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode) 0.8VCC2 Standard Min. 3.0 Typ. 5.0 VCC1 0 0 VCC2 Max. 5.5 Unit V V V V V
Symbol VCC1, VCC2 AVCC VSS AVSS VIH
VCC1
6.0 VCC2 VCC2
VIL
Input low "L" voltage
P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(2) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7(1), P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(2), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode) P0_0 to P0_7, P1_0 to P1_7 (in memory expansion mode and microprocessor mode)
0
0.2VCC2
V
0
0.2VCC1
0 0
0.2VCC2
0.16VCC2
NOTES: 1. VIH and VIL reference for P8_7 apply when P8_7 is used as a programmable input port. It does not apply when P8_7 is used as XCIN. 2. P11 to P15 are provided in the 144-pin package only.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 48 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 5.3
5. Electrical Characteristics
Recommended Operating Conditions (2/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified
Parameter Peak output high "H" current(2) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) Standard Min. Typ. Max. -10.0 Unit mA
Symbol
IOH(peak)
IOH(avg)
Average output high "H" current(1)
-5.0
mA
IOL(peak)
Peak output low "L" current(2)
10.0
mA
IOL(avg)
Average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, output low "L" P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, current(1) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3)
5.0
mA
NOTES: 1. Average output current is the average value within 100 ms. 2. A total IOL(peak) of P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 must be 80 mA or less. A total IOL(peak) of P3, P4, P5, P6, P7,P8_0 to P8_4, P12, and P13 must be 80 mA or less. A total IOH(peak) of P0, P1, P2, and P11 must be -40 mA or less. A total IOH(peak) of P8_6 to P8_7, P9, P10, P14, and P15 must be -40 mA or less. A total IOH(peak) of P3, P4, P5, P12, and P13 must be -40 mA or less. A total IOH(peak) of P6, P7, and P8_0 to P8_4 must be -40 mA or less. 3. P11 to P15 are provided in the 144-pin package only.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 49 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 5.4
5. Electrical Characteristics
Recommended Operating Conditions (3/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified)
Parameter CPU clock frequency (same frequency as f(BCLK)) Main clock input oscillation frequency Sub clock frequency On-chip oscillator frequency VCO clock frequency (PLL frequency synthesizer) PLL clock frequency Wait time to stabilize PLL frequency synthesizer VCC1 = 4.2 to 5.5V VCC1 = 3.0 to 5.5V VCC1 = 5.0V VCC1 = 3.3V 20 10 10 VCC1 = 4.2 to 5.5V VCC1 = 3.0 to 5.5V VCC1 = 4.2 to 5.5V VCC1 = 3.0 to 5.5V Standard Min. 0 0 0 0 32.768 1 80 32 24 5 10 Typ. Max. 32 24 32 24 50 Unit MHz MHz MHz MHz kHz MHz MHz MHz MHz ms ms
Symbol f(CPU) f(XIN) f(XCIN) f(Ring) f(VCO) f(PLL) tsu(PLL)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 50 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.5 Electrical Characteristics (1/3) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 32 MHz unless otherwise specified)
Parameter Output high "H" voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) Measurement Condition IOH = -5 mA Standard Min.
VCC2 - 2.0
Symbol VOH
Typ.
Max. VCC2
Unit V
IOH = -5 mA
VCC1 - 2.0
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7 IOH = -200 A VCC2 - 0.3 P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = -200 A VCC1 - 0.3 P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VOL Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "L" voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VT+ - VTHysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT8, ADTRG, CTS0 to CTS6, CLK0 to CLK6, TA0OUT to TA4OUT, NMI, KI0 to KI3, RXD0 to RXD6, SCL0 to SCL4, SDA0 to SDA4, INPC1_0 to INPC1_7, ISCLK0 to ISCLK2, ISRXD0 to ISRXD2, IEIN, CAN0IN, CAN1IN, CAN1WU RESET NOTE: 1. P11 to P15 are provided in the 144-pin package only. IOH = -1 mA No load applied No load applied IOL = 5 mA 3.0 2.5 1.6
VCC2
V
VCC1
VCC1
V V V
2.0
V
IOL = 200 A
0.45
V
IOL = 1 mA No load applied No load applied 0.2 0 0
2.0
V V V
1.0
V
0.2
1.8
V
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 51 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.6 Electrical Characteristics (2/3) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 32 MHz unless otherwise specified)
Parameter Input high "H" current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE Measurement Condition VI = 5 V Standard Min. Typ. Max. 5.0 Unit A
Symbol IIH
IIL
Input low "L" P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XIN XCIN In stop mode
VI = 0V
-5.0
A
RPULLUP Pull-up resistance
VI = 0V
30
50
167
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM data retention voltage
1.5 10 2.0
M M V
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 52 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.7 Electrical Characteristics (3/3) (VCC1 = VCC2 = 5.5 V, VSS = 0 V, Topr = 25C)
Measurement Condition(1) Flash memory version f(CPU) = 32 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode While flash memory is operating f(CPU) = 32 kHz In low-power consumption mode While flash memory is stopped(2) Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C Mask ROM version f(CPU) = 32 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C 32 19 12 1 30 50 Standard Min. Typ. Max. 32 19 12 2.6 430 45 Unit mA mA mA mA A
Symbol Parameter ICC Power supply current
30
A
50
A
0.8
5 50 45
A A mA mA mA mA A A
0.8
5 50
A A
NOTES: 1. In single-chip mode, leave the output pins open and connect the input pins to VSS. 2. Value is obtained when setting the FMSTP bit in the FMR0 register to 1 (flash memory stopped) and running the program on RAM.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 53 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.8 A/D Conversion Characteristics
(VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 32MHz unless otherwise specified) Symbol - INL Parameter Resolution Integral nonlinearity error Measurement Condition VREF = VCC1 VREF = VCC1 = VCC2 = 5 V AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, ANEX1 External op-amp connection mode DNL - - tCONV tCONV tSAMP VREF VIA Differential nonlinearity error Offset error Gain error VREF = VCC1 time(1)(2) 8 2.06 1.75 0.188 2 0 VCC1 VREF 10-bit conversion Sampling time(1) Standard Min. Typ. Max. 10 3 Unit Bits LSB
7 1 3 3 40
LSB LSB LSB LSB k s s s V V
RLADDER Resistor ladder 8-bit conversion time(1)(2) Reference voltage Analog input voltage
NOTES: 1. The value is obtained when AD frequency is at 16 MHz. Keep AD frequency at 16 MHz or lower. 2. With using the sample and hold function
Table 5.9
D/A Conversion Characteristics (VCC1 = VCC2 = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 32MHz unless otherwise specified)
Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (note 1) 4 10 Measurement Condition Standard Min. Typ. Max. 8 1.0 3 20 1.5 Unit Bits % s k mA
Symbol - - tsu RO IVREF
NOTE: 1. Measured when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if the VCUT bit in the AD0CON1 register is set to 0 (VREF not connected)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 54 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.10 Flash Memory Electrical Characteristics (VCC1 = 4.5 V to 5.5 V, 3.0 to 3.6 V, Topr = 0 to 60C unless otherwise specified)
Symbol - - - - Parameter Erase and program endurance(1) Word program time (16 bits) (VCC1 = 5.0 V, Topr = 25C) Lock bit program time Block erase time (VCC1 = 5.0 V, Topr = 25C) 4-Kbyte block 8-Kbyte block 32-Kbyte block 64-Kbyte block tps - Wait time to stabilize flash memory circuit Data hold time (Topr = -40 to 85C) 10 Measurement Condition Standard Min. 100 25 25 0.3 0.3 0.5 0.8 300 300 4 4 4 4 15 Typ. Max. Unit times s s s s s s s years
NOTE: 1. If erase and program endurance is n times (n = 100), each block can be erased n times. For example, if a 4Kbyte block A is erased after programming a word data 2,048 times, each to a different address, this counts as one erase and program time. Data can not be programmed to the same address more than once without erasing the block. (rewrite prohibited)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 55 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.11 Voltage Detection Circuit Electrical Characteristics (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, Topr = 25C unless otherwise specified)
Parameter Vdet4 detection voltage Vdet3 detection voltage Hardware reset 2 hold voltage Hardware reset 2 release voltage VCC1 = 3.0 V to 5.5 V Measurement Condition Standard Min. 3.3 Typ. 3.8 3.0 2.0 3.1 Max. 4.4 Unit V V V V
Symbol Vdet4 Vdet3 Vdet3s Vdet3r
NOTES: 1. Vdet4 > Vdet3 2. Vdet3r > Vdet3 is not guaranteed.
Table 5.12
Symbol td(P-R) td(S-R) td(E-A)
Power Supply Circuit Timing Characteristics
Parameter Wait time to stabilize internal supply voltage when power-on Wait time to release hardware reset 2 Start-up time for Vdet3 and Vdet4 detection circuit Measurement Condition VCC1 = 3.0 to 5.5 V VCC1 = Vdet3r to 5.5 V VCC1 = 3.0 to 5.5 V 6(1) Standard Min. Typ. Max. 2 20 20 Unit ms ms s
NOTE: 1. When VCC1 = 5 V
td(P-R) Wait time to stabilize internal supply voltage when power-on
Recommended operating voltage VCC1 td(P-R) CPU clock
td(S-R) Wait time to release hardware reset 2
VCC1
Vdet3r td(S-R)
CPU clock
td(E-A) Start-up time for Vdet3 and Vdet4 detection circuit
VC26, VC27 Vdet3 and Vdet4 detection circuit
Stop
Operating
td(E-A)
Figure 5.1
Power Supply Timing Diagram
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 56 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.13
Symbol tc tw(H) tw(L) tr tf
External Clock Input
Parameter External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rise time External clock fall time Standard Min. 31.25 13.75 13.75 5 5 Max. Unit ns ns ns ns ns
Table 5.14
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Count Source Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 40 40 Max. Unit ns ns ns
Table 5.15
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Gate Signal Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.16
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 200 100 100 Max. Unit ns ns ns
Table 5.17
Symbol tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 100 Max. Unit ns ns
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 57 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.18
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) i = 0 to 4 TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter Standard Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Table 5.19
Symbol tc(TA)
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Parameter TAiIN input cycle time Standard Min. 800 200 200 Max. Unit ns ns ns
tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time
i = 0 to 4
Table 5.20
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Count Source Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 5.21
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.22
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 58 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.23
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG input cycle time (required for trigger) ADTRG input low ("L") pulse width Standard Min. 1000 125 Max. Unit ns ns
Table 5.24
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 to 6
Serial Interface
Parameter CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TXDi output delay time TXDi output hold time RXDi input setup time RXDi input hold time 0 70 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns
Table 5.25
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 1
Intelligent I/O Communication Function (Groups 0 and 1)
Parameter ISCLKi input cycle time ISCLKi input high ("H") pulse width ISCLKi input low ("L") pulse width ISTXDi output delay time ISTXDi output hold time ISRXDi input setup time ISRXDi input hold time 0 100 100 Standard Min. 600 300 300 100 Max. Unit ns ns ns ns ns ns ns
Table 5.26
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Intelligent I/O Communication Function (Group 2)
Parameter ISCLK2 input cycle time ISCLK2 input high ("H") pulse width ISCLK2 input low ("L") pulse width ISTXD2 output delay time ISTXD2 output hold time ISRXD2 input setup time ISRXD2 input hold time 0 150 100 Standard Min. 600 300 300 180 Max. Unit ns ns ns ns ns ns ns
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 59 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.27
Symbol tw(INH) tw(INL)
External Interrupt INTi Input (Edge Sensitive)
Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min. 250 250 Max. Unit ns ns
i = 0 to 8(1) NOTE: 1. INT6 to INT8 are provided in the 144-pin package only.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 60 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.28
Symbol
tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK)
Memory Expansion mode and Microprocessor Mode
Parameter Data input access time (RD standard) Data input access time (AD standard, CS standard) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, when accessing a space with the multiplexed bus) Data input setup time RDY input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 26 26 30 0 0 0 25 Standard Min. Max. (note 1) (note 1) (note 1) (note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA)
NOTE: 1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) = 109 x m f(BCLK) x 2 109 x n f(BCLK) 109 x m f(BCLK) x 2 109 x p f(BCLK) x 2 - 35 [ns] (if external bus cycle is a + b, m = (b x 2) + 1)
tac1(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, n = a + b)
tac2(RD-DB) =
- 35 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, p = {(a + b - 1) x 2} + 1)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 61 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.29
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR)
Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(3) Address output hold time (WR standard)(3) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR WR output width standard)(3) -5 (note 2) (note 1) (note 2) -5 18 standard)(3) Chip-select signal output hold time (WR standard)(3) -3 0 See Figure 5.2 (note 1) 18 -3 0 (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 15 [ns]
th(WR-AD) =
- 10 [ns]
th(WR-CS) =
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations.
td(DB-WR) tw(WR) = = 109 x m f(BCLK) 109 x n f(BCLK) x 2 - 20 [ns] (if external bus cycle is a + b, m = b) - 15 [ns] (if external bus cycle is a + b, n = (b x 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 62 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.30
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD)
Memory Expansion Mode and Microprocessor Mode (when accessing external memory space with multiplexed bus)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(5) Address output hold time (WR standard)(5) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(5) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output float start time -2 (note 3) (note 4) 8 -5 (note 2) (note 1) 18 See Figure 5.2 -5 18 standard)(5) Chip-select signal output hold time (WR standard)(5) -3 (note 1) (note 1) 18 -3 (note 1) (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 x m f(BCLK) x 2 109 x n f(BCLK) x 2 109 x n f(BCLK) x 2 - 10 [ns]
th(WR-AD) =
- 10 [ns]
th(RD-CS)
=
- 10 [ns]
th(WR-CS) =
- 10 [ns]
th(WR-DB) =
- 15 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) = - 25 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) = - 20 [ns] (if external bus cycle is a + b, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) = - 20 [ns] (if external bus cycle is a + b, n = a)
5. tc [ns] is added when recovery cycle is inserted.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 63 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
30 pF
Note 1
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
Figure 5.2
P0 to P15 Measurement Circuit
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 64 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1=VCC2=5V
tc
XIN input
tr tw(H) tc(TA) tw(TAH) tf tw(L)
TAiIN input
tw(TAL) tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/ decrement select input) In event counter mode TAiIN input (count on falling edge) TAiIN input (count on rising edge) In event counter mode with two-phase pulse input
tc(TA) th(TIN-UP) tsu(UP-TIN)
TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH)
CLKi ISCLKi
tw(CKL) th(C-Q)
TXDi ISTXDi
td(C-Q) tsu(D-C)
RXDi ISRXDi
tw(INL)
th(C-D)
INTi input NMI input
2 CPU clock cycles + 300 ns or more ("L" width)
tw(INH)
2 CPU clock cycles + 300 ns or more
Figure 5.3
VCC1 = VCC2 = 5 V Timing Diagram (1/4)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 65 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode and Microprocessor Mode
BCLK
(Separate bus)
RD
WR, WRL, WRH
(Separate bus)
(Multiplexed bus)
RD
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK) th(BCLK-RDY)
BCLK
th(BCLK-HOLD) tsu(HOLD-BCLK)
HOLD Input
HLDA Output
td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z
P0, P1, P2, P3, P4, P5_0 to P5_2
Measurement Conditions - VCC1 = VCC2 = 4.2 to 5.5 V - Input high and low voltage: VIH = 4.0 V, VIL = 1.0 V - Output high and low voltage: VOH = 2.5 V, VOL = 2.5 V
Figure 5.4
VCC1 = VCC2 = 5 V Timing Diagram (2/4)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 66 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space)
Read Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max(1) th(BCLK-CS) -3ns.min
VCC1=VCC2=5V
CSi
tcyc td(BCLK-AD) 18ns.max(1) th(RD-CS) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-RD) 18ns.max th(RD-AD) 0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2) th(BCLK-RD) -5ns.min
DBi
Hi-Z
tsu(DB-BCLK) 26ns.min(1)
NOTES: 1. Values guaranteed only when the MCU is used stand-alone. A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) + 1) tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a + b, n = a + b)
th(RD-DB) 0ns.min
Write Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min
CSi
tcyc td(BCLK-AD) 18ns.max th(WR-CS)(3) th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-WR) 18ns.max tw(WR)(3) th(WR-AD)(3)
WR,WRL,WRH
th(BCLK-WR) -5ns.min td(DB-WR)(3) th(WR-DB)(3)
DBi NOTES: Measurement Conditions: 3. Varies with operation frequency: - VCC1 = VCC2 = 4.2 to 5.5 V td(DB-WR) = (tcyc x m - 20) ns.min - Input high and low voltage: VIH = 2.5 V, VIL = 0.8 V ( if external bus cycle a + b, m = b) - Output high and low voltage: VOH = 2.0 V, VOL = 0.8 V th(WR-DB) = (tcyc / 2 - 15) ns.min th(WR-AD) = (tcyc / 2 - 10) ns.min th(WR-CS) = (tcyc / 2 - 10) ns.min 109 tw(WR) = (tcyc / 2 x n - 15) ns.min tcyc= (if external bus cycle a + b, n = (b x 2) - 1) f(BCLK)
Figure 5.5
VCC1 = VCC2 = 5 V Timing Diagram (3/4)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 67 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Read Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
VCC1=VCC2=5V
ALE
td(BCLK-CS) 18ns.max tcyc th(RD-CS)(1) td(AD-ALE)(1) th(ALE-AD)(1) tsu(DB-BCLK) 26ns.min th(BCLK-CS) -3ns.min
CSi
ADi /DBi
td(BCLK-AD) 18ns.max
Address
tdz(RD-AD) 8ns.max tac2(RD-DB)(1)
Data input
Address
th(RD-DB) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
tac2(AD-DB)(1) th(RD-AD)(1) td(BCLK-RD) 18ns.max th(BCLK-RD) -5ns.min
RD
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) - 1) tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b, p = {(a + b - 1) x 2} + 1)
Write Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
ALE
td(BCLK-CS) 18ns.max tcyc
th(BCLK-CS)
th(WR-CS)(2) -3ns.min
CSi
td(AD-ALE)(2) th(ALE-AD)(2)
ADi /DBi
td(BCLK-AD) 18ns.max
Address
Data output
td(DB-WR)(2) th(WR-DB)(2)
Address
ADi BHE
td(BCLK-WR) 18ns.max th(BCLK-WR) -5ns.min
th(BCLK-AD) -3ns.min
WR,WRL,WRH
th(WR-AD)(2)
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min th(WR-DB) = (tcyc / 2 - 15) ns.min td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b, m = (b x 2) - 1) Measurement Conditions: 109 - VCC1 = VCC2 = 4.2 to 5.5 V tcyc= - Input high and low voltage VIH = 2.5 V, VIL = 0.8 V f(BCLK) - Output high and low voltage VOH = 2.0 V, VOL = 0.8 V
Figure 5.6
VCC1 = VCC2 = 5 V Timing Diagram (4/4)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 68 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.31 Electrical Characteristics (1/3)
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 24 MHz unless otherwise specified) Symbol VOH Output high "H" voltage Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VOL Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "L" voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VT+ - VTHysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT8, ADTRG, CTS0 to CTS6, CLK0 to CLK6, TA0OUT to TA4OUT, NMI, KI0 to KI3, RXD0 to RXD6, SCL0 to SCL4, SDA0 to SDA4, INPC1_0 to INPC1_7, ISCLK0 to ISCLK2, ISRXD0 to ISRXD2, IEIN, CAN0IN, CAN1IN, CAN1WU RESET NOTE: 1. P11 to P15 are provided in the 144-pin package only. IOH = -0.1 mA No load applied No load applied IOL = 1 mA Measurement Condition IOH = -1 mA Standard Min.
VCC2 - 0.6
Typ.
Max. VCC2
Unit V
VCC1 - 0.6
VCC1
2.7 2.5 1.6
VCC1
V V V
0.5
V
IOL = 0.1 mA No load applied No load applied 0.2 0 0
0.5
V V V
1.0
V
0.2
1.8
V
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 69 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.32 Electrical Characteristics (2/3) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 24 MHz unless otherwise specified)
Parameter Input high P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "H" current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE Input low "L" current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XIN XCIN In stop mode 2.0 Measurement Condition VI = 3 V Standard Min. Typ. Max. 4.0 Unit A
Symbol IIH
IIL
VI = 0V
-4.0
A
RPULLUP Pull-up resistance
VI=0V
40
90
500
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM data retention voltage
3.0 20.0
M M V
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 70 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.33 Electrical Characteristics (3/3) (VCC1 = VCC2 = 3.3 V, VSS = 0 V, Topr = 25C)
Measurement Condition(1) Flash memory version f(CPU) = 24 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode While flash memory is operating f(CPU) = 32 kHz In low-power consumption mode While flash memory is stopped(2) Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C Mask ROM version f(CPU) = 24 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C 23 17 11 1 30 45 Standard Min. Typ. Max. 23 17 11 2.6 430 33 Unit mA mA mA mA A
Symbol Parameter ICC Power supply current
30
A
45
A
0.8
5 50 33
A A mA mA mA mA A A
0.8
5 50
A A
NOTES: 1. In single-chip mode, leave the output pins open and connect the input pins to VSS. 2. Value is obtained when setting the FMSTP bit in the FMR0 register to 1 (flash memory stopped) and running the program on RAM.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 71 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.34 A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 24MHz unless otherwise specified)
Parameter Resolution Integral nonlinearity error (8-bit) Differential nonlinearity error (8-bit) Offset error (8-bit) Gain error (8-bit) VREF = VCC1 time(1)(2) 8 4.9 3 0 VCC1 VREF 8-bit conversion Measurement Condition VREF = VCC1 VREF = VCC1 = VCC2 = 3.3 V Standard Min. Typ. Max. 10 2 1 2 2 40 Unit Bits LSB LSB LSB LSB k s V V
Symbol - INL DNL - - tCONV VREF VIA
RLADDER Resistor ladder Reference voltage Analog input voltage
NOTES: 1. The value when AD frequency is at 10 MHz. Keep AD frequency at 10 MHz or lower. If f(CPU) (=fAD) is 24 MHz, divide f(CPU) by 3 to make it 8 MHz. The conversion time in this case is 6.1 s. 2. Sample and hold function is not available.
Table 5.35
D/A Conversion Characteristics (VCC1 = VCC2 = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 24MHz unless otherwise specified)
Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (note 1) 4 10 Measurement Condition Standard Min. Typ. Max. 8 1.0 3 20 1.0 Unit Bits % s k mA
Symbol - - tsu RO IVREF
NOTE: 1. Measurement when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if VCUT bit in the AD0CON1 register is set to 0 (VREF not connected)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 72 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.36
Symbol tc tw(H) tw(L) tr tf
External Clock Input
Parameter External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rise time External clock fall time Standard Min. 41 18 18 5 5 Max. Unit ns ns ns ns ns
Table 5.37
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Count Source Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 40 40 Max. Unit ns ns ns
Table 5.38
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Gate Signal Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.39
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 200 100 100 Max. Unit ns ns ns
Table 5.40
Symbol tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 100 Max. Unit ns ns
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 73 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.41
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) i = 0 to 4 TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter Standard Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Table 5.42
Symbol tc(TA)
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Parameter TAiIN input cycle time Standard Min. 2 500 500 Max. Unit s ns ns
tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time
i = 0 to 4
Table 5.43
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Count Source Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 5.44
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 5.45
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 74 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.46
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG input cycle time (required for trigger) ADTRG input low ("L") pulse width Standard Min. 1000 125 Max. Unit ns ns
Table 5.47
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 to 6
Serial Interface
Parameter CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TXDi output delay time TXDi output hold time RXDi input setup time RXDi input hold time 0 70 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns
Table 5.48
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 1
Intelligent I/O Communication Function (Groups 0 and 1)
Parameter ISCLKi input cycle time ISCLKi input high ("H") pulse width ISCLKi input low ("L") pulse width ISTXDi output delay time ISTXDi output hold time ISRXDi input setup time ISRXDi input hold time 0 100 100 Standard Min. 600 300 300 100 Max. Unit ns ns ns ns ns ns ns
Table 5.49
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Intelligent I/O Communication Function (Group 2)
Parameter ISCLK2 input cycle time ISCLK2 input high ("H") pulse width ISCLK2 input low ("L") pulse width ISTXD2 output delay time ISTXD2 output hold time ISRXD2 input setup time ISRXD2 input hold time 0 150 100 Standard Min. 600 300 300 180 Max. Unit ns ns ns ns ns ns ns
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 75 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.50
Symbol tw(INH) tw(INL)
External Interrupt INTi Input (Edge Sensitive)
Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min. 250 250 Max. Unit ns ns
i = 0 to 8(1) NOTE: 1. INT6 to INT8 are provided in the 144-pin package only.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 76 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.51
Symbol
tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK)
Memory Expansion Mode and Microprocessor Mode
Parameter Data input access time (RD standard) Data input access time (AD standard, CS standard) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, when accessing a space with the multiplexed bus) Data input setup time RDY input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 30 40 60 0 0 0 25 Standard Min. Max. (note 1) (note 1) (note 1) (note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA)
NOTE: 1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) = 109 x m f(BCLK) x 2 109 x n f(BCLK) 109 x m f(BCLK) x 2 109 x p f(BCLK) x 2 - 35 [ns] (if external bus cycle is a + b, m = (b x 2) + 1)
tac1(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, n = a + b)
tac2(RD-DB) =
- 35 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, p = {(a + b - 1) x 2} + 1)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 77 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.52
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR)
Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(3) Address output hold time (WR standard)(3) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR WR output width standard)(3) 0 (note 2) (note 1) (note 2) -5 18 standard)(3) Chip-select signal output hold time (WR standard)(3) -3 0 See Figure 5.2 (note 1) 18 -3 0 (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 20 [ns]
th(WR-AD) =
- 15 [ns]
th(WR-CS) =
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations.
td(DB-WR) tw(WR) = = 109 x m f(BCLK) 109 x n f(BCLK) x 2 - 20 [ns] (if external bus cycle is a + b, m = b) - 15 [ns] (if external bus cycle is a + b, n = (b x 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 78 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 5.53
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD)
Memory Expansion Mode and Microprocessor Mode (when accessing external memory space with multiplexed bus)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(5) Address output hold time (WR standard)(5) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(5) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output float start time -2 (note 3) (note 4) 8 0 (note 2) (note 1) 18 See Figure 5.2 -5 18 standard)(5) Chip-select signal output hold time (WR standard)(5) -3 (note 1) (note 1) 18 -3 (note 1) (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 x m f(BCLK) x 2 109 x n f(BCLK) x 2 109 x n f(BCLK) x 2 - 10 [ns]
th(WR-AD) =
- 15 [ns]
th(RD-CS)
=
- 10 [ns]
th(WR-CS) =
- 10 [ns]
th(WR-DB) =
- 20 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) = - 25 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) = - 20 [ns] (if external bus cycle is a + b, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) = - 20 [ns] (if external bus cycle is a + b, n = a)
5. tc [ns] is added when recovery cycle is inserted.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 79 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1=VCC2=3.3V
tc
XIN input
tr tw(H) tc(TA) tw(TAH) tf tw(L)
TAiIN input
tw(TAL) tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/ decrement select input) In event counter mode TAiIN input (count on falling edge) TAiIN input (count on rising edge) In event counter mode with two-phase pulse input
tc(TA) th(TIN-UP) tsu(UP-TIN)
TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH)
CLKi ISCLKi
tw(CKL) th(C-Q)
TXDi ISTXDi
td(C-Q) tsu(D-C)
RXDi ISRXDi
tw(INL)
th(C-D)
INTi input NMI input
2 CPU clock cycles + 300 ns or more ("L" width)
tw(INH)
2 CPU clock cycles + 300 ns or more
Figure 5.7
VCC1 = VCC2 = 3.3 V Timing Diagram (1/4)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 80 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
VCC1=VCC2=3.3V
Memory Expansion Mode and Microprocessor Mode
BCLK
(Separate bus)
RD
WR, WRL, WRH
(Separate bus)
(Multiplexed bus)
RD
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK) th(BCLK-RDY)
BCLK
th(BCLK-HOLD) tsu(HOLD-BCLK)
HOLD Input
HLDA Output
td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z
P0, P1, P2, P3, P4, P5_0 to P5_2
Measurement Conditions -VCC1 = VCC2 = 3.0 to 3.6 V -Input high and low voltage: VIH = 2.4 V, VIL = 0.6 V -Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
Figure 5.8
VCC1 = VCC2 = 3.3 V Timing Diagram (2/4)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 81 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space)
Read Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max(1)
VCC1=VCC2=3.3V
th(BCLK-CS) -3ns.min
CSi
tcyc td(BCLK-AD) 18ns.max(1) th(RD-CS) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-RD) 18ns.max th(RD-AD) 0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2) th(BCLK-RD) -5ns.min
DBi
Hi-Z
tsu(DB-BCLK) 30ns.min(1)
NOTES: 1. Values guaranteed only when the MCU is used stand-alone. A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) + 1) tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a + b, n = a + b)
th(RD-DB) 0ns.min
Write Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min
CSi
tcyc td(BCLK-AD) 18ns.max th(WR-CS)(3) th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-WR) 18ns.max tw(WR)(3) th(WR-AD)(3)
WR,WRL,WRH
th(BCLK-WR) 0ns.min td(DB-WR)(3) th(WR-DB)(3)
DBi NOTES: Measurement Conditions: 3. Varies with operation frequency: - VCC1 = VCC2 = 3.0 to 3.6 V td(DB-WR) = (tcyc x m - 20) ns.min - Input high and low voltage: VIH = 1.5 V, VIL = 0.5 V ( if external bus cycle a + b, m = b) - Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V th(WR-DB) = (tcyc / 2 - 20) ns.min th(WR-AD) = (tcyc / 2 - 15) ns.min th(WR-CS) = (tcyc / 2 - 10) ns.min 109 tw(WR) = (tcyc / 2 x n - 15) ns.min tcyc= (if external bus cycle a + b, n = (b x 2) - 1) f(BCLK)
Figure 5.9
VCC1 = VCC2 = 3.3 V Timing Diagram (3/4)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 82 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Read Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
VCC1=VCC2=3.3V
ALE
td(BCLK-CS) 18ns.max tcyc th(RD-CS)(1) td(AD-ALE)(1) th(ALE-AD)(1) tsu(DB-BCLK) 30ns.min th(BCLK-CS) -3ns.min
CSi
ADi /DBi
td(BCLK-AD) 18ns.max
Address
tdz(RD-AD) 8ns.max tac2(RD-DB)(1)
Data input
Address
th(RD-DB) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
tac2(AD-DB)(1) th(RD-AD)(1) td(BCLK-RD) 18ns.max th(BCLK-RD) -5ns.min
RD
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) - 1) tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b, p = {(a + b - 1) x 2} + 1)
Write Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
ALE
td(BCLK-CS) 18ns.max tcyc th(WR-CS)(2) -3ns.min
th(BCLK-CS)
CSi
td(AD-ALE)(2) th(ALE-AD)(2)
ADi /DBi
td(BCLK-AD) 18ns.max
Address
Data output
td(DB-WR)(2) th(WR-DB)(2)
Address
ADi BHE
td(BCLK-WR) 18ns.max th(BCLK-WR) 0ns.min
th(BCLK-AD) -3ns.min
WR,WRL,WRH
th(WR-AD)(2)
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(WR-AD) = (tcyc / 2 - 15) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min th(WR-DB) = (tcyc / 2 - 20) ns.min td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b, m = (b x 2) - 1) Measurement Conditions: 109 - VCC1 = VCC2 = 3.0 to 3.6 V tcyc= - Input high and low voltage VIH = 1.5 V, VIL = 0.5 V f(BCLK) - Output high and low voltage VOH = 1.5 V, VOL = 1.5 V
Figure 5.10
VCC1 = VCC2 = 3.3 V Timing Diagram (4/4)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 83 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g
HD *1 108 D 73 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
109
72
c1 HE E
c
Reference Symbol
*2
Dimension in Millimeters
Terminal cross section
1 ZD
A2
A
36 Index mark F
ZE
144
37
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
*3 e y
bp
x
Detail F
Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.17 0.22 0.27 0.20 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.10 1.25 1.25 0.35 0.5 0.65 1.0
JEITA Package Code P-LQFP100-14x14-0.50
RENESAS Code PLQP0100KB-A
Previous Code 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.] 0.6g
HD *1 D
75
51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
76
50
A1
bp b1
HE
E
c
Reference Dimension in Millimeters Symbol
*2
c1
c
Terminal cross section
1 Index mark ZD
25 F
ZE
100
26
A2
A
D E A2 HD HE A A1 bp b1 c c1
c
A1
y e
*3
bp
L L1 Detail F
x
e x y ZD ZE L L1
Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 8 0 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 84 of 85
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Appendix 1. Package Dimensions
JEITA Package Code P-QFP100-14x20-0.65
RENESAS Code PRQP0100JB-A
Previous Code 100P6S-A
MASS[Typ.] 1.6g
HD *1 80
D 51
81
50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
ZE
Reference Dimension in Millimeters Symbol
100
31
1
ZD
Index mark
30 F
c
A2
L e y *3 bp Detail F
D E A2 HD HE A A1 bp c e y ZD ZE L
Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.25 0.3 0.4 0.13 0.15 0.2 0 10 0.5 0.65 0.8 0.10 0.575 0.825 0.4 0.6 0.8
A
REJ03B0127-0151 Rev.1.51 Jul 31, 2008 Page 85 of 85
A1
REVISION HISTORY
Rev. 0.50 1.00 Date Dec.16, 04 Jul.14, 05
M32C/87 Group Datasheet
Description
Page
- - - -
Summary New Document
M32C/87A and M32C/87B added Package code changed: 144P6Q-A to PLQP0144KA-A, 100P6Q-A to PLQP0100KB-A, 100P6S-A to PRQP0100JB-A "Low Voltage Detection Reset" changed to "Brown-out Detection Reset" Overview * Table 1.2 M32C/87 Group Performance (144-Pin Package) M32C/87A and M32C/87B performance added to the CAN module performance; Power Consumption performance released * Table 1.2 M32C/87 Group Performance (100-Pin Package) M32C/87A and M32C/87B performance added to the CAN module performance; Power Consumption performance released * Figure 1.1 M32C/87 Group Block Diagram Note 4 deleted; note 5 added * Figure 1.3 Pin Assignment for 144-Pin Package Note 15 added * Table 1.4 Pin Characteristics for 144-Pin Package Note 1 added * Figure 1.4 Pin Assignment for 100-Pin Package Note 19 added * Figure 1.5 Pin Assignment for 100-Pin Package Note 15 added * Table 1.5 Pin Characteristics for 100-Pin Package Note 1 added * Table 1.6 Pin Description Note 2 added Memory * Figure 3.1 Memory Map Note 3 changed Special Function Register (SFR) * The RLVL register Value after reset modified * The IIO0IR to IIO11IR registers Value after reset modified * Name of the registers assosiated to Intelligent I/O changed * The G0RB register Value after reset modified * The G1BCR0 and G1BCR1 registers Value after reset modified * The G0CR register Value after reset modified * Note added to the CAN-associated registers * The TCSPR register Value after reset modified; note 1 added * The AD00 register Value after reset modified * The PSC register Value after reset modified * The PS2 register Value after reset modified * The PCR register Value after reset modified * The PSD1 register Value after reset modified * The PCR register Value after reset modified Electrical Characteristics * Table 5.2 Electrical Characteristics Parameter f(BCLK) and its values added; min. and max. values for f(RING) added * Table 5.3 Electrical Characteristics VOH values modified; RPULLUP value modified * Table 5.3 Electrical Characteristics (Continued) Measurement Condition and standard values for ICC added and some released * Table 5.6 Flash Memory Version Electrical Characteristics Word Program Time and Lock bit Program Time values modified; parameter AllUnlocked-Block-Erase Time deleted; note 1 deleted * Table 5.10 Memory Expansion Mode and Microprocessor Mode tac1(RD-DB) expression on note 1 modified; tac2(RD-DB) expression on note 1 added
2 3 4 7 8 11 12 13 17 22 26 26 27 to 30 27 27 29 32 to 37 40 41 42 42 43 44 45 48 49 50 52 54
A-1
REVISION HISTORY
Rev. Date Page 57 58 60 61
M32C/87 Group Datasheet
Description Summary
Electrical Characteristics * Table 5.22 Memory Expansion Mode and Microprocessor Mode th(WRDB) expression on note 1 modified * Table 5.23 Memory Expansion Mode and Microprocessor Mode th(WRDB) expression on note 1 modified; th(ALE-AD) expression on note 4 modified * Figure 5.3 Vcc1=Vcc2=5V Timing Diagram (1) tac1(RD-DB) expression on note 2 modified; th(WR-DB) and tw(ER) expressions on note 3 modified; tcyc expression added * Figure 5.4 Vcc1=Vcc2=5V Timing Diagram (2) tac2(RD-DB) and tac2(ADDB) expressions on note 1 modified; th(ALE-AD) expressions on notes 1 and 2 modified; td(DB-WR) expression on note 2 modified; tcyc expression added * Figure 5.5 Vcc1=Vcc2=5V Timing Diagram (3) NMI input diagram added * Table 5.24 Electrical Characteristics VOH values changed;RPULLUP and Icc values modified * Table 5.25 A/D Conversion Characteristics tCONV value modified * Table 5.28 Memory Expansion Mode and Microprocessor Mode tac1(RD-DB) expression on note 1 modified; tac2(RD-DB) expression on note 1 added * Table 5.40 Memory Expansion Mode and Microprocessor Mode th(BCLK-AD), th(BCLK-CS) and th(BCLK-RD) values modified; th(WR-AD) expression on note 1 modified * Table 5.41 Memory Expansion Mode and Microprocessor Mode th(BCLK-AD), th(BCLK-CS) and th(BCLK-RD) values modified; th(WR-AD) expression on note 1 modified; th(ALE-AD) expression on note 4 modified * Figure 5.7 Vcc1=Vcc2=3.3V Timing Diagram (1) th(BCLK-AD), th(BCLKCS) and th(BCLK-RD) values modified; tac1(AD-DB) expression on note 2 modified; th(WR-DB), th(WR-AD) and tw(WR) expression on note 3 modified; tcyc expression added * Figure 5.8 Vcc1=Vcc2=3.3V Timing Diagram (2) tac2(RD-DB) and tac1(AD-DB) expressions on note 1 modified; th(ALE-AD) expressions on notes 1 and 2 modified; td(WR-AD), td(DB-WR) and th(WR-DB) expressions on note 2 modified; tcyc expression added * Figure 5.9 Vcc1=Vcc2=3.3V Timing Diagram (3) NMI input diagram added
62 64 65 66 69 70 71
72
73 1.01 Aug. 29, 05 17 29 29 49
Overview * Tables 1.6 Pin Description Intelligent I/O functions modified
Special Function Register (SFR) * The G1BCR0 register Value after reset modified * The G1BCR1 register Value after reset modified Electrical Characteristics * Table 5.3 Electrical Characteristics ICC standard value modified
A-2
REVISION HISTORY
Rev. 1.50 Date Oct 20, 2007 Page All
M32C/87 Group Datasheet
Description Summary
All in this manual * Descriptions and formats unified * Notation of numbers changed (e.g. 002 00b, FF16 FFh) * Notation of pin name changed (e.g. RTP00 RTP_0, A15(/D15) [A15/D15]) * [Term changed] Serial I/O Serial interface Clock synchronous serial I/O mode Clock synchronous mode Clock asynchronous serial I/O mode Clock asynchronous mode Clock synchronous variable length Variable data length clock synchronous Voltage detection circuit Power supply voltage detection function Low voltage detection interrupt Vdet4 detection interrupt Brown-out detection reset Vdet3 detection function
Overview * Header SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER RENESAS MCU * 1.1 Features title added; 1.1 Applications changed to 1.1.1 Applications 2 * 1.2 Performance Overview changed to 1.1.2 Specifications 2-5 * Tables 1.1 to 1.4 Structure, descriptions in Specification field, NOTE, and value partially revised or deleted * Real-Time Port Item deleted; ROM Correction Function Item added 8 * 1.3 Block Diagram moved following the 1.2 Product List 6-7 * 1.2 Product List Tables revised; NOTE 1 added 9, 14, 15 * Figures 1.3 to 1.5 Arrows for VSS and VCC deleted; NOTES partially modified 11,17 * Tables 1.9 and 1.13 CLKOUT pin moved from Bus Control Pin column to Control Pin column 19-22 * Tables 1.15 to 1.19 Descriptions revised; NOTE 1 added
1
26 34-39 45 27 34
Memory * Text partially modified SFR * Tables 4.8 to 4.13 NOTE "Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers." added * Table 4.19 The PSL5 register added to the Address field of 03BBh item; the PSL7 register added to the Address field of 03BFh item * [Register names changed] 002Fh Low Voltage Detection Interrupt Register Vdet4 Detection Interrupt Register 01C1h UART5 Bit Rate Register UART5 Baud Rate Register 01C9h UART6 Bit Rate Register UART6 Baud Rate Register 01D0h UART5, UART6 Transmit/Receive Control Register 2 UART5, UART6 Transmit/Receive Control Register 01DBh to 01D8h Pulse Output Data Register RTP Output Buffer Register 0303h to 0302h Timer A1-1 Register Timer A11 Register 0305h to 0304h Timer A2-1 Register Timer A21 Register 0307h to 0306h Timer A4-1 Register Timer A41 Register 0340h Count Start Flag Count Start Register 0341h Clock Prescaler Reset Flag Clock Prescaler Reset Register
41 42
A-3
REVISION HISTORY
Rev. Date Page 42
M32C/87 Group Datasheet
Description Summary
SFR * [Register names changed] 0342h One-Shot Start Flag One-Shot Start Register 0344h Up-Down Flag Up/Down Select Register * [Value After Reset changed] 000Fh WDC 000X XXX2 00XX XXXXb 002Fh D4INT 0016 XX00 0000b 007Bh IIO6IC XX00 X0002 XXXX X000b 00EFh G0CR XX00 X0112 0000 X011b 00FEh G0IRF 0016 0000 XXXXb 013Eh G1IRF 0016 0000 XXXXb 01C7h to 01C6h U5RB XXXX XXXX XXXX 0XXX2 XXXXh 01CFh to 01CEh U6RB XXXX XXXX XXXX 0XXX2 XXXXh 038Fh to 0382h AD07 to AD01 XXXX16 00XXh Electrical Characteristics * [Term changed] Low Voltage Reset Hardware Reset 2 Low Voltage Detection Vdet3 and Vdet4 detection circuit * Table 5.1 Description in Condition field of Pd (Power consumption) partially modified * Tables 5.2 to 5.9 f(BCLK) is changed to f(CPU) * Table 5.4 Description added in Parameter field of f(CPU); f(VCO) added * Tables 5.5 to 5.7 and Tables 5.31 to 5.33 Description in XCOUT and Hysteresis in Parameter fields partially modified * Table 5.7 and 5.33 Structure and standard values revised; items in Measurement Condition and NOTE added * Table 5.8 Description in Parameter field and NOTE partially modified * Table 5.9 and 5.10 Description in Parameter field and NOTE partially modified * Tables 5.11 and 5.36 Description in Parameter field and standard value partially modified * Tables 5.19 and 5.42 added * Table 5.24 Values revised; Table 5.25 and 5.26 added * Table 5.27 Titles modified; NOTE added * Table 5.28 moved to the last table in Timing Requirements * Table 5.29 NOTE 3 added; Table 26.30 NOTE 5 added * Figures 5.3 to 5.6 Order rearranged; measurement condition modified * Table 5.31 to 5.35 f(BCLK) revised to f(CPU) * Table 5.47 Values revised; Table5.48 and 5.49 added * Table 5.50 Titles modified; NOTE added * Table 5.51 Table moved to the last table in Timing Requirements * Table 5.52 NOTE 3 added; Table 5.53 NOTE 5 added * Figures 5.7 to 5.10 Order rearranged All in this manual [description modified] * Title of group tables "(current table number / total tables)" added Overview * 1.5 Pin Descriptions Chapter and table title changed to Pin Functions * Table 1.17 Supply voltage for AN0_0 to AN0_7, AN2_0 to AN2_7 modified
27 27 29 31 31 32 34 34 44
47 50-53 50 51,69 53,71 54 54,55 56,73 58,74 59 60 61 62-63 65-68 69-72 75 76 77 78-79 80-83 1.51 Jul 31, 2008
-
19 21
A-4
REVISION HISTORY
Rev. Date Page 46
M32C/87 Group Datasheet
Description Summary
Special Function Registers (SFRs) * Table 4.20 A value of After Reset column in 03FFh modified
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